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single - phase active and apparent energy metering ic data sheet ade7763 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. speci fications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high accuracy; supports iec 61036/60687, iec62053 - 21, and iec62053 - 22 on - chip digital integrator enables direct interface - to - current sensors with di/dt output a pga in the current channel allows direct interface to shunts and current transformers active and apparent energy, sampled waveform, and current and voltage rms less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25c positive - only energy accumulation mode available on - chip user programmable threshold for l ine voltage surge and sag and psu supervisory digital calibration for power, phase, and input offset on - chip temperature sensor (3c typical) spi? - compatible serial interface pulse output with programmable frequency interrupt request pin ( i rq ) and status register reference 2.4 v with external overdrive capability single 5 v supply, low power (25 mw typical) general description the ade7763 1 features proprietary adcs and fixed function dsp for high accuracy over large variations in environm ental conditions and time. the ade7763 incorporates two second - order, 16 - bit - ? adcs, a digital integrator (on ch1), reference circuitry, a temperature sensor, and all the signal processing required to perform active and apparent energy measurements, line - voltage period measurements, and rms calculation on the voltage and current channels. the selectable on - chip digital integrator provides direct interface to di/dt current sensors such as rogowski coils, eliminating the need for an external analog integrat or and resulting in excellent long - term stability and precis e phase matching between the current and the voltage channels. the ade7763 provides a serial interface to read data and a pulse output frequency (cf) that is proportional to the active p owe r. var ious system calibration features such as channel offset correction, phase calibration, and power calibration ensure high accuracy. the part also detects short duration, low or high voltage variations. the positive - only accumulation mode gives the option to accumulate energy only when positive power is detected. an internal no - load threshold ensures that the part does not exhibit any creep when there is no load. the zero - crossing output (zx) produces a pulse that is synchronized to the zero - crossing point of the line voltage. this signal is used internally in the line cycle active and apparent energy accumulation modes, which enables faster calibration. the interrupt status register indicates the nature of the interrupt, and the interrupt enable register cont rols which event produces an output on the irq pin, an open - drain, active low logic output. the ade7763 is available in a 20 - lead ssop package. f unctional b lock d iagram 04481-a-001 avdd reset dvdd dgnd temp sensor adc adc dfc x 2 ade7763 lpf2 multiplier integrator clkin clkout din dout sclk ref in/out cs irq agnd apos[15:0] vagain[11:0] vadiv[7:0] irmsos[11:0] vrmsos[11:0] lpf3 lpf3 wgain[11:0] dt registers and serial interface cfnum[11:0] cfden[11:0] 2.4v reference 4k phcal[5:0] hpf1 lpf1 v1p v1n v2n v2p pga pga zx sag cf wdiv[7:0] % % |x| figure 1. 1 u.s. patents 5,745,323; 5,7 60,617; 5,862 ,069; 5,872,469 .
ade7763 data sheet rev . c | page 2 of 56 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 terminology ...................................................................................... 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 analog inputs .............................................................................. 14 di/dt current sensor and digital integrator ........................... 15 zero - crossing detection ........................................................... 16 period measurement .................................................................. 17 power suppl y monitor ............................................................... 17 line voltage sag detection ....................................................... 18 peak detection ............................................................................ 18 int errupts ..................................................................................... 19 temperature measurement ....................................................... 20 analog - to - digital conversion .................................................. 20 channel 1 adc .......................................................................... 21 channel 2 adc .......................................................................... 23 phase compensation .................................................................. 24 ac tive power calculation .......................................................... 25 energy calculation ..................................................................... 27 power offset calibration ........................................................... 29 energy - to - frequency conversion ............................................ 29 line cycle energy accumulation mode ................................. 31 positive - only accumulation mode ......................................... 31 no - load threshold .................................................................... 31 apparent power calculation ..................................................... 32 apparent energy calcu lation ................................................... 33 line apparent energy accumulation ...................................... 34 energies scaling .......................................................................... 35 calibrating an energy meter .................................................... 35 clkin frequency ...................................................................... 44 suspending functionality .......................................................... 45 checksum register ..................................................................... 45 serial interface ............................................................................ 45 registers ........................................................................................... 48 register descriptions ..................................................................... 51 communication register .......................................................... 51 mode register (0x09) ................................................................. 51 interrupt status register (0x0b), reset interrupt status register (0x0c), interrupt enable register (0x0a) ............... 53 ch1os register (0x0d) ............................................................ 54 outline dimensions ....................................................................... 55 ordering guide .......................................................................... 55
data sheet ade7763 rev. c | page 3 of 56 r evision h istory 1 /1 3 rev. b to rev. c changes to figure 1 ........................................................................... 1 moved revision history section ..................................................... 3 changes to table 2 ............................................................................ 6 changes to table 4 ............................................................................ 9 changes to figure 24 ...................................................................... 14 changes to zero - crossing detection section ............................. 16 changes to period measurement section .................................... 17 changes to peak level record section ......................................... 18 change to figure 37 ........................................................................ 19 changes to figure 43, channel 1 sampl ing section, and channel 1 rms calculation section ........................................... 22 changes to channel 1 rms offset compensation section and channel 2 sampling section .......................................................... 23 changes to channel 2 rms calculation section and channel 2 rms offset compensation section .............................................. 24 changes to energy ca lculation section ....................................... 27 changes to power offset calibration section ............................. 29 changes to positive - only accumulation mode section ............ 31 changes to serial interface section .............................................. 45 changes to table 9 .......................................................................... 48 change to table 12, bit 1 description .......................................... 53 changes to ordering guide ........................................................... 55 7 /0 9 rev. a to rev. b changes to zero crossing detection section ............................. 1 5 changes to period measurement section .................................... 16 changes to channel 1 rms offset calculation section ............ 22 changes to channel 1 rms offset compensation section ...... 22 changes to figure 48 ...................................................................... 23 changes to chan nel 2 rms calculation section ........................ 23 changes to table 11, bit 15 description ...................................... 51 changes to table 12, bit 4 description ........................................ 52 10 /04 data s heet c hanged from rev. 0 to rev. a changes to period measurement s ection .................................. 16 changes to temperature measurement s ection ....................... 19 chan ge to energy - to - frequency conversion s ection ............. 2 8 update to figure 61 ....................................................................... 29 change to apparent energy calculation s ection ..................... 32 change to d escription of aehf and vaehf b its ................... 5 2 changes to ordering guide ......................................................... 54 4/04 revision 0: initial version
ade7763 data sheet rev . c | page 4 of 56 specifications av dd = d v dd = 5 v 5%, agnd = dgnd = 0 v, on - chip reference, clkin = 3.579545 mhz xtal, t min to t max = C 40c to +85c. table 1 . specifications 1, 2 parameter spec unit test conditions/comments energy measurement accuracy active power m easurement error clkin = 3.579545 mhz channel 1 range = 0.5 v full scale channel 2 = 300 mv rms/60 hz, gain = 2 gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic ra nge 1000 to 1 gain = 8 0.1 % typ over a dynamic range 1000 to 1 channel 1 range = 0.25 v full scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 channel 1 range = 0.125 v full scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.2 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 active power measurement bandwidth 14 k hz phase error 1 between channels 0.05 max line frequency = 45 hz to 65 hz, hpf on ac power supply rejection 1 avdd = dv dd = 5 v + 175 mv rms/120 hz output frequency variation (cf) 0.2 % typ channel 1 = 20 mv rms, gain = 16, range = 0.5 v channel 2 = 300 mv rms/60 hz, gain = 1 dc power supply rejection 1 avdd = dvdd = 5 v 250 mv dc output frequency variation (cf) 0.3 % typ channel 1 = 20 mv rms/60 hz, gain = 16, range = 0.5 v channel 2 = 300 mv rms/60 hz, gain = 1 irms measurement error 0.5 % typ over a dynamic range 100 to 1 irms measurement bandwidth 14 khz vrms measurement error 0.5 % typ over a dynamic range 20 to 1 vrms measurement bandwidth 140 hz analog inputs 3 see the analog inputs section maximum signal levels 0.5 v max v1p, v1n, v2n, and v2p to agnd input impedance (dc) 390 k min bandwidth 14 khz clkin/256, clkin = 3.579545 mhz gain error 1 , 3 external 2.5 v reference, gain = 1 on channels 1 and 2 ch annel 1 range = 0.5 v full scale 4 % typ v1 = 0.5 v dc range = 0.25 v full scale 4 % typ v1 = 0.25 v dc range = 0.125 v full scale 4 % typ v1 = 0.125 v dc channel 2 4 % typ v2 = 0.5 v dc offset error 1 32 mv max gain 1 channel 1 13 mv max ga in 16 32 mv max gain 1 channel 2 13 mv max gain 16 waveform sampling sampling clkin/128, 3.579545 mhz/128 = 27.9 ksps channel 1 see the channel 1 sampling section signal - to - noise plus distortion 62 db ty p 150 mv rms/60 hz, range = 0.5 v, gain = 2 bandwidth ( C 3 db) 14 khz clkin = 3.579545 mhz channel 2 see the channel 2 sampling section signal - to - noise plus distortion 60 db typ 150 mv rms/60 hz, gain = 2 bandw idth ( C 3 db) 140 hz clkin = 3.579545 mhz
data sheet ade7763 rev. c | page 5 of 56 parameter spec unit test conditions/comments reference input ref in/out input voltage range 2.6 v max 2.4 v + 8% 2.2 v min 2.4 v C 8% input capacitance 10 pf max on - chip reference nominal 2.4 v at ref in/out pin reference error 200 mv max current source 10 a max output impedance 3.4 k? min temperature coefficient 30 ppm/c typ clkin all specifications clkin of 3.579545 mhz input clock frequency 4 mhz max 1 mhz min logic inputs reset , din, sclk, clkin, and cs input high voltage, v inh 2.4 v min dvdd = 5 v 10% input low voltage, v inl 0.8 v max dvdd = 5 v 10% input current, i in 3 a max typically 10 na, v in = 0 v to dvdd input capacitance, c in 10 pf max logic outputs sag and irq open - dr ain outputs, 10 k? pull - up resistor output high voltage, v oh 4 v min i source = 5 ma output low voltage, v ol 0.4 v max i sink = 0.8 ma zx and dout output high voltage, v oh 4 v min i source = 5 ma output low voltage, v ol 0.4 v max i sink = 0.8 ma cf output high voltage, v oh 4 v min i source = 5 ma output low voltage, v ol 1 v max i sink = 7 ma power supply for specified performance avdd 4.75 v min 5 v C 5% 5.25 v max 5 v + 5% dvdd 4.75 v min 5 v C 5% 5.25 v max 5 v + 5% aidd 3 ma max typical ly 2.0 ma didd 4 ma max typically 3.0 ma 1 see the terminology section for explanation of specifications. 2 see the plots in the typical performance characteristics section. 3 see the analog inputs section. +2.1v 1.6ma i oh i ol 200 a c l 50pf 04481-a-002 to output pin figure 2 . load circuit for timing specifications
ade7763 data sheet rev. c | page 6 of 56 timing characteristics av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.579545 mhz xtal, t min to t max = ?40c to +85c. table 2. timing characteristics 1, 2 parameter spec unit test conditions/comments write timing t 1 50 ns min cs falling edge to first sclk falling edge. t 2 50 ns min sclk logic high pulse width. t 3 50 ns min sclk logic low pulse width. t 4 10 ns min valid data setup time before falling edge of sclk. t 5 5 ns min data hold time after sclk falling edge. t 6 4 s min minimum time between the end of data byte transfers. t 7 3200 ns min minimum time between byte transfers during a serial write. t 8 100 ns min) cs hold time after sclk falling edge. read timing t 9 3 4 s min minimum time between read command (i.e., a write to communication register) and data read. t 10 50 ns min minimum time between data byte transfers during a multibyte read. t 11 30 ns min data access time after sclk rising edge following a write to the communication register. t 12 4 100 ns max bus relinquish time after falling edge of sclk. 10 ns min t 13 5 100 ns max bus relinquish time after rising edge of cs . 10 ns min 1 sample tested during initial release and after any redesign or process change that could affect this parameter. all input sign als are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 v. 2 see figure 3, figure 4, and the serial interface section. 3 minimum time between read command and data read for all registers except waveform register, which is t 9 = 500 ns min. 4 measured with the load circuit in figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v. 5 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circ uit in figure 2. the measure d number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time quoted in the timing characteris tics is the true bus relinquish time of the part and is independent of the bus loading. din sclk cs t 2 t 3 t 1 t 4 t 5 t 7 t 6 t 8 command byte most significant byte least significant byte 1 0 a4a5 a3 a2 a1 a0 db7 db0 db7 db0 t 7 04481-a-003 figure 3. serial write timing sclk cs t 1 t 10 t 13 0 0 a4a5 a3 a2 a1 a0 db0 db7 db0 db7 din dout t 11 t 11 t 12 command byte most significant byte least significant byte t 9 04481-a-004 figure 4. serial read timing
data sheet ade7763 rev. c | page 7 of 56 absolute maximum rat ings t a = 25c, unless otherwise noted . table 3 . parameter rating av dd to agnd C 0.3 v to +7 v dvdd to dgnd C 0.3 v to +7 v dvdd to avdd C 0.3 v to +0.3 v analog input voltage to agnd v1p, v1n, v2p, and v2n C 6 v to +6 v reference input voltage to agnd C 0.3 v to avdd + 0.3 v digital input voltage to dgnd C 0.3 v to dvdd + 0.3 v digital output voltage to dgnd C 0.3 v to dvdd + 0.3 v operating temperature range industrial C 40c to +85c storage temperature range C 65c to +150c junction temperature 150c 20- lead s sop, power dissipation 450 mw ja thermal impedance 112c/w lead temperature, soldering vapor phase (60 s) 215c infrared (15 s) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and function al operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd cauti on esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, pe rmanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ade7763 data sheet rev . c | page 8 of 56 terminology measurement error the error associated wi th the energy measurement made by the ade7763 is defined by the following formula: percent error = ? ? ? ? ? ? ? ? ? energy true energy true ade7763 register energy 100% phase error between channels the digital integrator and the high - pass filter (hpf) in channel 1 have a nonideal phase response . to offset this phase response and equalize the phase response between channels, two phase - correction networks are placed in channel 1: one for the digital integrator and the other for the hpf. the phase correction networks correct the phase response of t he corresponding component and ensure a phase match between channel 1 (current) and channel 2 (voltage) to within 0.1 over a range of 45 hz to 65 hz with the digital integrator off. with the digital integrator on, the phase is corrected to within 0.4 o ver a range of 45 hz to 65 hz. power supply rejection this quantifies the ade7763 measurement error as a percentage of the reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (5 v) is taken. a second readin g is obtained with the same input signal levels when an ac (175 mv rms/120 hz) signal is introduced to the supplies. any error introduced by this ac signal is expressed as a percentage of the reading see the measurement error definition. for the dc psr m easurement, a reading at nominal supplies (5 v) is taken. a second reading is obtained with the same input signal levels when the supplies are varied 5%. any error introduced is again expressed as a percentage of the reading. adc offset error the dc offse t associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs still see a dc analog input signal. the magnitude of the offset depends on the gain and input range selection see the typical performance characteristics section . however, when hpf1 is switched on, the offset is removed from channel 1 (current) and the power calculation is not affected by this offset. the offsets can be removed by performing an offset calibration see the analog inputs section. gain error the difference between the measured adc output code (minus the offset) and the ideal output code see the channel 1 adc and channel 2 adc sections. it is measured for each of the input ranges on channel 1 (0.5 v, 0.25 v, and 0.125 v). the difference is expressed as a percentage of the ideal code.
data sheet ade7763 rev. c | page 9 of 56 pin configuration an d function descripti ons v2n 6 v2p 7 agnd 8 ref in/out 9 dgnd 10 clkin irq sag zx cf 15 14 13 12 11 ade7763 top view (not to scale) dvdd 2 avdd 3 v1p 4 v1n 5 dout sclk cs clkout 19 18 reset 1 din 20 17 16 04481-a-005 figure 5 . pin configuration (ss op package) table 4 . pin function descriptions pin no. mnemonic description 1 reset reset pin 1 . a logic low on this pin holds the adcs and digital circuitry (including the serial interface) in a reset condition. 2 dvdd digital power supply. this pin provides the supply voltage for the digital circuitry. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled to dgnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 3 avdd analog power supply. this pin provides the supply voltage for the analog circuitry. the supply should be maintained at 5 v 5% for specified operation. minimize power supply ripple and noise at this pin by using proper decouplin g. the typical performance graphs show the power supply rejection performance. this pin should be decoupled to agnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 4, 5 v1p, v1n analog inputs for channel 1. this channel is intended for use with a di/dt current transducer, i.e., a rogowski coil or another current sensor such as a shunt or current transformer (ct). these inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 v, 0.25 v, and 0.1 25 v, depending on the full - scale selection see the analog inputs section. channel 1 also has a pga with gain selections of 1, 2, 4, 8, or 16. the maximum signal level at these pins with respect to agnd is 0.5 v. both inputs have internal esd protection circuitry and can sustain an overvoltage of 6 v without risk of permanent damage. 6, 7 v2n, v2p analog inputs for channel 2. this channel is intended for use with the voltage transducer. these inputs are fully differential voltage inputs with a maximum differential signal level of 0.5 v. channel 2 also has a pga with gain selections of 1, 2, 4, 8, or 16. the maximum signal level at these pins with respect to agnd is 0.5 v. both inputs have internal esd protection circuitry and ca n sustain an overvoltage of 6 v without risk of permanent damage. 8 agnd analog ground reference. this pin provides the ground reference for the analog circuitry, i.e. , adcs and reference. this pin should be tied to the analog ground plane or to the quie test ground reference in the system. use this quiet ground reference for all analog circuitry, such as antialiasing filters and current and voltage transducers. to minimize ground noise around the ade7763, connect the quiet ground plane to the digital gro und plane at only one point. it is acceptable to place the entire device on the analog ground plane. 9 ref in/out access to the on - chip voltage reference. the on - chip reference has a nominal value of 2.4 v 8% and a typical temperature coefficient of 30 ppm/c. an external reference source can also be connected at this pin. in either case, this pin should be decoupled to agnd with a 1 0 f capacitor in parallel with a 100nf ceramic capacitor. 10 dgnd digital ground reference. this pin provides the ground reference for the digital circuitry, i.e., multiplier, filters, and digital - to - frequency converter. because the digital return currents in the ade7763 are small, it is acceptable to connect this pin to the analog ground plane of the system. however, high b us capacitance on the dout pin could result in noisy digital current, which could affect performance. 11 cf calibration frequency logic output. the cf logic output gives active power information. this output is intended to be used for operational and cali bration purposes. the full - scale output frequency can be adjusted by writing to the cfden and cfnum registers see the energy - to - frequency conversion section. 12 zx voltage waveform (channel 2) zero - crossing output. this output tog gles logic high and logic low at the zero crossing of the differential signal on channel 2 see the zero - crossing detection section. 13 sag this open - drain logic output goes active low when either no zero crossing s are detected or a low voltage threshold (channel 2) is crossed for a specified duration see the line voltage sag detection section.
ade7763 data sheet rev . c | page 10 of 56 pin no. mnemonic description 14 irq interrupt request output. this is an active low, open - drain logic outpu t. maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples see the interrupts section. 15 clkin master clock for adcs and digital sign al processing. an external clock can be provided at this logic input. alternatively, a parallel resonant at crystal can be connected across clkin and clkout to provide a clock source for the ade7763. the clock frequency for specified operation is 3.579545 mhz. ceramic load capacitors between 22 pf and 33 pf should be used with the gate oscillator circuit. refer to the crystal manufacturers data sheet for load capacitance requirements. 16 clkout a crystal can be connected across this pin and clkin, as desc ribed for pin 15, to provide a clock source for the ade7763. the clkout pin can drive one cmos load when either an external clock is supplied at clkin or a crystal is being used. 17 cs chip select 1 . part of the 4 - wire spi serial interface. this active low logic input allows the ade7763 to share the serial bus with several other devices see the serial interface section. 18 sclk serial clock input for the synchronous serial interfac e 1 . all serial data transfers are synchronized to this clock see the serial interface section. the sclk has a schmitt - trigger input for use with a clock source that has a slow edge transition time, such as an opto - isolator output. 19 dout data output for the serial interface. data is shifted out at this pin upon the rising edge of sclk. this logic output is normally in a high impedance state, unless it is driving data onto the serial data bus see th e serial interface section. 20 din data input for the serial interface. data is shifted in at this pin upon the falling edge of sclk see the serial interface section. 1 it is recommended to drive the reset , sclk, and cs pins with either a push - pull w it hout an external series resistor or with an open - collector with a 10 k ? pull - up pull - down resistors are not recommended because under some conditions, they may interact with internal circuitry.
data sheet ade7763 rev. c | page 11 of 56 typical performance characteristics full-scale current (%) error (%) 0.1 ?0.6 ?0.2 ?0.3 ?0.4 ?0.5 0.1 0 0.4 0.3 0.2 ?0.1 1 10 100 04481-a-006 gain = 1 integrator off internal reference ?40c, pf = 0.5 +85c, pf = 0.5 +25c, pf = 0.5 +25c, pf = 1 figure 6. active energy error as a percentage of reading (gain = 1) over power factor with internal reference and integrator off ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-007 gain = 8 integrator off internal reference +85c, pf = 1 +25c, pf = 1 ?40c, pf = 1 figure 7. active energy as a percentage of reading (gain = 8) over temperature with internal reference and integrator off ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-008 gain = 8 integrator off internal reference +85c, pf = 0.5 +25c, pf = 0.5 ?40c, pf = 0.5 +25c, pf = 1 figure 8. active energy error as a percentage of reading (gain = 8) over power factor with internal reference and integrator off ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-009 gain = 8 integrator off external reference +85c, pf = 1 ?40c, pf = 1 +25c, pf = 1 figure 9. active energy error as a percentage of reading (gain = 8) over temperature with external reference and integrator off ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-010 gain = 8 integrator off external reference +85c, pf = 0.5 +25c, pf = 0.5 ?40c, pf = 0.5 +25c, pf = 1 figure 10. active energy error as a percentage of reading (gain = 8) over power factor with external reference and integrator off ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (%) full-scale current (%) 0.1 10 1 100 04481-a-080 gain = 8 integrator off internal reference 5.25v 5.00v 4.75v figure 11. active energy error as a percentage of reading (gain = 8) over power supply with internal reference and integrator off
ade7763 data sheet rev. c | page 12 of 56 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 error (%) 45 47 49 51 53 55 57 59 61 63 65 frequency (hz) 04481-a-012 gain = 8 integrator off internal reference pf = 0.5 pf = 1 figure 12. active energy error as a percentage of reading (gain = 8) over frequency with internal reference and integrator off ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-013 gain = 8 integrator off internal reference pf = 1 pf = 0.5 figure 13. irms error as a percentage of reading (gain = 8) with internal referenc e and integrator off ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (%) full-scale voltage (%) 1 10 100 04481-a-020 gain = 1 external reference figure 14. vrms error as a percentage of reading (gain = 1) with external reference ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-016 gain = 8 integrator on internal reference +85c, pf = 0.5 +25c, pf = 1 ?40c, pf = 0.5 +25c, pf = 0.5 figure 15. active energy error as a percentage of reading (gain = 8) over power factor with internal reference and integrator on ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (%) full-scale current (%) 0.1 10 1 100 04481-a-015 gain = 8 integrator on internal reference +85c, pf = 1 +25c, pf = 1 ?40c, pf = 1 figure 16. active energy error as a percentage of reading (gain = 8) over temperature with external reference and integrator on ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 error (%) 45 47 49 51 53 55 57 59 61 63 65 frequency (hz) 04481-a-017 gain = 8 integrator on internal reference pf = 0.5 pf = 1 figure 17. active energy error as a percentage of reading (gain = 8) over frequency with internal reference and integrator on
data sheet ade7763 rev. c | page 13 of 56 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (%) full-scale current (%) 0.1 10 1 100 04481-a-081 gain = 8 integrator on internal reference 5.25v 5.00v 4.75v figure 18. active energy error as a percentage of reading (gain = 8) over power supply with internal reference and integrator on ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (%) full-scale current (%) 0.1 10 1 100 04481-a-019 gain = 8 integrator on internal reference pf = 0.5 pf = 1 figure 19. irms error as a percentage of reading (gain = 8) with internal referenc e and integrator on 0 2 4 6 8 10 hits 12 14 16 ?15 ?10 ?5 0 5 10 15 20 ch1 offset (0p5v_1x) (mv) 04481-a-021 figure 20. channel 1 offset (gain = 1) v dd 10 ?f 10 ?f 10 ?f 100nf 100nf avdd dvdd reset din dout sclk cs clkout clkin irq sag zx cf agnd dgnd v1p v1n v2n v2p ref in/out u1 ade7763 to spi bus (used only for calibration) 22pf 22pf y1 3.58mhz not connected u3 ps2501-1 i di/dt current sensor 100 ? 1k ? 33nf 33nf 100 ? 1k ? 33nf 33nf 1k ? 33nf 600k ? 110v 1k ? 33nf 100nf channel 1 gain = 8 channel 2 gain = 1 to frequency counter 04481-a-022 fi g ure 21. test circui t for performance curves with inte g rator on ct turn ratio = 1800:1 channel 2 gain = 1 rb 10 ? 1.21 ? gain 1 (ch1) 1 8 not connected v dd 10 ? f10 ? f 100nf 100nf din dout sclk cs clkout clkin irq sag zx cf agnd dgnd v1p v1n v2n v2p ref in/out u1 ade7763 to spi bus (used only for calibration) 22pf 22pf y1 3.58mhz u3 ps2501-1 i current transformer 1k ? 33nf 1k ? 33nf 1k ? 33nf 600k ? rb 110v 1k ? 33nf 10 ? f 100nf to frequency counter 04481-a-023 avdd dvdd reset figure 22. test circuit for performance curves with integrator off
ade7763 data sheet rev . c | page 14 of 56 theory of operation analog inputs the ade7763 has two fully differential voltage input channels. the maximum differential input voltage for input pairs v1p/v1n and v2p/v2n is 0.5 v. i n addition, the maximum signal level on analog inputs for v1p/v1n and v2p/v2n is 0.5 v with respect to agnd. each analog input channel has a programmable gain amplifier (pga) with possible gain selections of 1, 2, 4, 8, and 16. the gain selections are mad e by writing to the gain register see figure 24 . bits 0 to 2 select the gain for the pga in channel 1; the gain selection for the pga in channel 2 is made via bits 5 to 7. figure 23 shows h ow a gain selection for channel 1 is made using the gain register. v1p v1n v in k v in + gain[7:0] 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 gain (k) selection offset adjust ( 50mv) ch1os[7:0] bits 0 to 5: sign magnitude coded offset correction bit 6: not used bit 7: digital integrator (on = 1, off = 0; default off) 04481-a-024 figure 23 . pga in channel 1 in addition to the pga, channel 1 also has a full - scale input range selection for the adc. the adc analog input range selection is als o made using the gain register see figure 24 . as previously mentioned, the maximum differential input voltage is 0.5 v. however, by using bits 3 and 4 in the gain register, the maximum adc input voltage can be set t o 0.5 v, 0.25 v, or 0.125 v. this is achieved by adjusting the adc reference see the reference circuit section. table 5 summarizes the maximum differential input signal level on channel 1 fo r the various adc range and gain selections. table 5 . maximum input signal levels for channel 1 max signal channel 1 adc input range selection 0.5 v 0.25 v 0.125 v 0.5 v gain = 1 ? ? 0.25 v gain = 2 gain = 1 ? 0.125 v gain = 4 gain = 2 gain = 1 0.0625 v gain = 8 gain = 4 gain = 2 0.0313 v gain = 16 gain = 8 gain = 4 0.0156 v ? gain = 16 gain = 8 0.00781 v ? ? gain = 16 gain register* channel 1 and channel 2 pga control 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 addr: 0x0f * register contents show power-on defaults pga 2 gain select 000 = 1 001 = 2 010 = 4 01 1 = 8 100 = 16 pga 1 gain select 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 channel 1 full-scale select 00 = 0.5v 01 = 0.25v 10 = 0.125v 04481-a-025 figure 24 . analog gain regis ter it is also possible to adjust offset errors on channel 1 and channel 2 by writing to the offset correction registers (ch1os and ch2os, respectively). these registers allow channel offsets in the range 20 mv to 50 mv (depending on the gain setting) to be removed. note that it is not necessary to perform an offset correction in an energy measurement application if hpf in channel 1 is switched on. figure 25 shows the effect of offsets on the real power calculation. as seen from figure 25 , an offset on channel 1 and channel 2 contributes a dc component after multiplication. because this dc component is extracted by lpf2 to generate the active (real) power information, the offsets contribute an error to the active power calculation. this problem is easily avoided by enabling hpf in channel 1. by removing the offset from at least one channel, no error component is generated at dc by the multiplication. error terms at cos( t) are removed by lpf2 and by integrat ion of the active power signal in the active energy register (aenergy[23:0]) see the energy calculation section.
data sheet ade7763 rev. c | page 15 of 56 dc component (including error term) is extracted by the lpf for real power calculation frequency (rad/s) i os ? v v os ? i v os ? i os v ? i 2 0 2 ? ? 04481-a-026 figure 25. effect of channel offsets on the real power calculation the contents of the offset correction registers are 6-bit, sign and magnitude coded. the weight of the lsb depends on the gain setting, i.e., 1, 2, 4, 8, or 16. table 6 shows the correctable offset span for each of the gain settings and the lsb weight (mv) for the offset correction registers. the maximum value that can be written to the offset correction registers is 31dsee figure 26. figure 26 shows the relationship between the offset correction register contents and the offset (mv) on the analog inputs for a gain of 1. to perform an offset adjustment, connect the analog inputs to agnd; there should be no signal on either channel 1 or channel 2. a read from ch annel 1 or channel 2 using the waveform register indicates the offset in the channel. this offset can be canceled by writing an equal and opposite offset value to the channel 1 offset register, or an equal value to the channel 2 offset register. the offset correction can be confirmed by performing another read. note that when adjusting the offset of channel 1, the digital integrator and the hpf should be disabled. table 6. offset correction rangechannels 1 and 2 gain correctable span lsb size 1 50 mv 1.61 mv/lsb 2 37 mv 1.19 mv/lsb 4 30 mv 0.97 mv/lsb 8 26 mv 0.84 mv/lsb 16 24 mv 0.77 mv/lsb ch1os[5:0] sign + 5 bits +50mv offset adjust 0x3f 0x00 0x1f ?50mv 0mv sign + 5 bits 01,1111b 11,1111b 04481-a-027 figure 26. channel 1 offset correction range (gain = 1) the current and voltage rms offsets can be adjusted with the irmsos and vrmsos registerssee the channel 1 rms offset compensation and channel 2 rms offset compensation sections. di/dt current sensor and digital integrator a di/dt sensor detects changes in magnetic field caused by ac current. figure 27 shows the principle of a di/dt current sensor. magnetic field created by current (directly proportional to current) + emf (electromotive force) ? induced by changes in magnetic flux density (di/dt) 04481-a-028 figure 27. principle of a di/dt current sensor the flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. changes in the magnetic flux density passing through a conductor loop generate an electromotive force (emf) between the two ends of the loop. the emf is a voltage signal that is proportional to the di/dt of the current. the voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. the current signal must be recovered from the di/dt signal before it can be used. an integrator is therefore necessary to restore the signal to its original form. the ade7763 has a built-in digital integrator to recover the current signal from the di/dt sensor. the digital integrator on channel 1 is switched off by default when the ade7763 is powered up. setting the msb of ch1os register turns on the integrator. figure 28, figure 29, figure 30, and figure 31 show the magnitude and phase response of the digital integrator. frequency (hz) 10 gain (db) 0 ?10 ?20 ?30 ?40 ?50 10 2 10 3 04481-a-029 figure 28. combined gain response of the digital integrator and phase compensator
ade7763 data sheet rev. c | page 16 of 56 frequency (hz) 10 2 10 3 04481-a-030 ?88.0 phase (degrees) ?88.5 ?89.0 ?89.5 ?90.0 ?90.5 figure 29. combined phase response of the digital integrator and phase compensator frequency (hz) ?1.0 ?6.0 40 70 45 gain (db) 50 55 60 65 ?1.5 ?2.0 ?2.5 ?3.5 ?4.5 ?5.5 ?3.0 ?4.0 ?5.0 04481-a-031 figure 30. combined gain response of the digital integrator and phase compensator (40 hz to 70 hz) ?89.75 ?89.80 ?89.85 ?89.90 ?89.95 ?90.00 frequency (hz) phase (degrees) 40 45 70 50 55 60 65 ?90.05 ?90.10 ?89.70 04481-a-032 figure 31. combined phase response of the digital integrator and phase compensator (40 hz to 70 hz) note that the integrator has a C20 db/dec attenuation and approximately a C90 phase shift. when combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. the di/dt sensor has a 20 db/dec gain. it also generates significant high frequency noise, necessitating a more effective antialiasing filter to avoid noise due to aliasingsee the antialias filter section. when the digital integrator is switched off, the ade7763 can be used directly with a conventional current sensor such as a current transformer (ct) or with a low resistance current shunt. zero-crossing detection the ade7763 has a zero-crossing detection circuit on channel 2. this zero crossing is used to produce an external zero-crossing signal (zx), which is used in the calibration mode (see the calibrating an energy meter section). this signal is also used to initiate a temperature measurement (see the temperature measurement section). figure 32 shows how the zero-crossing signal is generated from the output of lpf1. ? 1, ? 2, ? 1, ? 8, ? 16 adc 2 reference 1 lpf1 f ? 3db = 140hz ?63% to +63% fs pga2 {gain[7:5]} v2p v2n v 2 zero crossing zx to multiplier 2.32 @ 60hz 1.0 0.93 zx v2 lpf1 04481-a-033 figure 32. zero-crossing detection on channel 2 the zx signal goes logic high upon a positive-going zero crossing and logic low upon a negative-going zero crossing on channel 2. the zx signal is generated from the output of lpf1. lpf1 has a single pole at 140 hz (@ clkin = 3.579545 mhz). as a result, there is a phase lag between the analog input signal v2 and the output of lpf1. the phase response of this filter is shown in the channel 2 sampling section. the phase lag response of lpf1 results in a time delay of approximately 1.14 ms (@ 60 hz) between the zero crossing on the analog inputs of channel 2 and the rising or falling edge of zx. zero-crossing detection also drives the zx flag in the interrupt status register. the zx flag is set to logic 1 on the rising and falling edge of the voltage waveform. it remains high until the status register is read with reset. an active low in the irq output appears if the corresponding bit in the interrupt enable register is set to logic 1. the flag in the interrupt status register and the irq output are set to their default values when reset (rststatus) is read in the interrupt status register. zero-crossing timeout zero-crossing detection has an associated timeout register, zxtout. this unsigned, 12-bit register is decremented (1 lsb)
data sheet ade7763 rev. c | page 17 of 56 every 128/clkin seconds. the register is reset to its user- programmed, full-scale value when a zero crossing on channel 2 is detected. the default power-on value in this register is 0xfff. if the internal register decrements to 0 before a zero crossing is detected and the dissag bit in the mode register is logic 0, the sag pin goes active low. the absence of a zero crossing is also indicated on the irq pin if the zxto enable bit in the interrupt enable register is set to logic 1. irrespective of the enable bit setting, the zxto flag in the interrupt status register is always set when the internal zxtout register is decremented to 0 see the interrupts section. the zxout register, address 0x1d, can be written to and read from by the usersee the serial interface section. the resolution of the register is 128/clkin seconds per lsb; therefore, the maximum delay for an interrupt is 0.15 seconds (128/clkin 2 12 ). figure 33 shows the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than clkin/128 zxtout seconds. 12-bit internal register value zxtout channel 2 zxto detection bit 04481-a-034 figure 33. zero-crossing timeout detection period measurement the ade7763 provides the period measurement of the line. the period register is an unsigned, 16-bit register that is updated every period and always has an msb of zero. the formula for the period register is shown below: f clkin period ?? ? ? 324 16 where clkin is the crystal frequency (3.579545 mhz recommended), and f is the line frequency. when clkin = 3.579545 mhz, the resolution of this register is 2.2 s/lsb, which represents 0.013% when the line frequency is 60 hz. when the line frequency is 60 hz, the value of the period register is approximately 7457d. the length of the register enables the measurement of line frequencies as low as 13.9 hz. the period register is stable at 1 lsb when the line is established and the measurement does not change. this filter is associated with a settling time of 1.8 seconds before the measurement is stable. see the calibrating an energy meter section for more on the period register. power supply monitor the ade7763 contains an on-chip power supply monitor. the analog supply (avdd) is continuously monitored. if the supply is less than 4 v 5%, the ade7763 will go into an inactive state and no energy will accumulate. this is useful to ensure correct device operation during power-up and power-down stages. in addition, built-in hysteresis and filtering help prevent false triggering due to noisy supplies. av dd 5v 4v 0v ade7763 power-on inactive state sag inactive active inactive time 04481-a-035 figure 34. on-chip power supply monitor as seen in figure 34, the trigger level is nominally set at 4 v. the tolerance on this trigger level is about 5%. the sag pin can also be used as a power supply monitor input to the mcu. the sag pin goes logic low when the ade7763 is in its inactive state. the power supply and decoupling for the part should be such that the ripple at avdd does not exceed 5 v 5%, as specified for normal operation.
ade7763 data sheet rev. c | page 18 of 56 line voltage sag detection in addition to detecting the loss of the line voltage when there are no zero crossings on the voltage channel, the ade7763 can also be programmed to detect when the absolute value of the line voltage drops below a peak value for a specified number of line cycles. this condition is illustrated in figure 35. sagcyc[7:0] = 0x04 3 line cycles sag reset high when channel 2 exceeds saglvl[7:0] full scale saglvl[7:0] sag channel 2 04481-a-036 figure 35. sag detection in figure 35 the line voltage falls below a threshold that has been set in the sag level register (saglvl[7:0]) for three line cycles. the quantities 0 and 1 are not valid for the sagcyc register, and the contents represent one more than the desired number of full line cycles. for example, if the dissag bit in the mode register is logic 0 and the sag cycle register (sagcyc[7:0]) contains 0x04, the sag pin goes active low at the end of the third line cycle for which the line voltage (channel 2 signal) falls below the threshold. as is the case when zero crossings are no longer detected, the sag event is also recorded by setting the sag flag in the interrupt status register. if the sag enable bit is set to logic 1, the irq logic output will go active lowsee the interrupts section. the sag pin goes logic high again when the absolute value of the signal on channel 2 exceeds the level set in the sag level register. this is shown in figure 35 when the sag pin goes high again during the fifth line cycle from the time when the signal on channel 2 first dropped below the threshold level. sag level set the contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from lpf1 after it is shifted left by one bit. for example, the nominal maximum code from lpf1 with a full-scale signal on channel 2 is 0x2518see the channel 2 sampling section. shifting one bit left gives 0x4a30. therefore, writing 0x4a to the sag level register puts the sag detection level at full scale. writing 0x00 or 0x01 puts the sag detection level at 0. the sag level register is compared to the most significant byte of a waveform sample after the shift left, and detection occurs when the contents of the sag level register are greater. peak detection the ade7763 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. figure 36 illustrates the behavior of the peak detection for the voltage channel. both channel 1 and channel 2 are monitored at the same time. pkv reset low when rststatus register is read vpklvl[7:0] v 2 read rststatus register pkv interrupt flag (bit 8 of status register) 04481-a-037 figure 36. peak level detection figure 36 shows a line voltage exceeding a threshold that has been set in the voltage peak register (vpklvl[7:0]). the voltage peak event is recorded by setting the pkv flag in the interrupt status register. if the pkv enable bit is set to logic 1 in the interrupt mask register, the irq logic output will go active low. similarly, the current peak event is recorded by setting the pki flag in the interrupt status registersee the interrupts section. peak level set the contents of the vpklvl and ipklvl registers are compared to the absolute value of channel 1 and channel 2, respectively, after they are multiplied by 2. for example, the nominal maximum code from the channel 1 adc with a full- scale signal is 0x2851ecsee the channel 1 sampling section. multiplying by 2 gives 0x50a3d8. therefore, writing 0x50 to the ipklvl register, for example, puts the channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value. writing 0x00 puts the channel 1 detection level at 0. peak level detection is done by comparing the contents of the ipklvl register to the incoming channel 1 sample. the irq pin indicates that the peak level is exceeded if the pki or pkv bits are set in the interrupt enable register (irqen [15:0]) at address 0x0a. peak level record the ade7763 records the maximum absolute value reached by channel 1 and channel 2 in two different registersipeak and vpeak, respectively. vpeak and ipeak are 24-bit, unsigned registers. these registers are updated at a rate of clkin/4 regardless of the waveform sampling rate. the contents of the vpeak register correspond to two times the maximum absolute value observed on the channel 2 input. the contents of ipeak represent the maximum absolute value observed on the channel 1
data sheet ade7763 rev. c | page 19 of 56 input. reading the rstvpeak and rstipeak registers clears their respective contents after the read operation. interrupts interrupts are managed through the interrupt status register (status[15:0]) and the interrupt enable register (irqen[15:0]). when an interrupt event occurs, the corresponding flag in the status register is set to logic 1see the interrupt status register section. if the enable bit for this interrupt in the interrupt enable register is logic 1, the irq logic output will go active low. the flag bits in the status register are set irrespective of the state of the enable bits. to determine the source of the interrupt, the system master (mcu) should perform a read from the status register with reset (rststatus[15:0]). this is achieved by carrying out a read from address 0ch. the irq output goes logic high after the completion of the interrupt status register read command see the interrupt timing section. when carrying out a read with reset, the ade7763 is designed to ensure that no interrupt events are missed. if an interrupt event occurs as the status register is being read, the event will not be lost and the irq logic output will be guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. see the next section for a more detailed description. using interrupts with an mcu figure 38 shows a timing diagram with a suggested imple- mentation of ade7763 interrupt management using an mcu. at time t 1 , the irq line goes active low, indicating that one or more interrupt events have occurred. tie the irq logic output to a negative edge-triggered external interrupt on the mcu. configure the mcu to start executing its interrupt service routine (isr) when a negative edge is detected on the irq line. after entering the isr, disable all interrupts by using the global interrupt enable bit. at this point, the mcu irq external interrupt flag can be cleared to capture interrupt events that occur during the current isr. when the mcu interrupt flag is cleared, a read from the status register with reset is carried out. this causes the irq line to reset to logic high (t 2 )see the interrupt timing section. the status register contents are used to determine the source of the interrupt(s) and, therefore, the appropriate action to be taken. if a subsequent interrupt event occurs during the isr, that event will be recorded by the mcu external interrupt flag being set again (t 3 ). upon the completion of the isr, the global interrupt mask is cleared (same instruction cycle) and the external interrupt flag causes the mcu to jump to its isr again. this ensures that the mcu does not miss any external interrupts. irq global interrupt mask set isr return global interrupt mask reset clear mcu interrupt flag read status with reset (0x0c) isr action (based on status contents) mcu interrupt flag set mcu program sequence 04481-a-038 t 1 t 2 t 3 jump to isr jump to isr figure 37. interrupt management sclk din dout irq t 11 t 11 t 9 t 1 read status register command status register contents db7 db7db0 cs 000 0 0101 db0 04481-a-039 figure 38. interrupt timing
ade7763 data sheet rev . c | page 20 of 56 interrupt timing review the serial interface section before reading this section. as previously described, when the irq output goes low, the mcu isr will read the interrupt status register to determine the source of the interrupt. when reading the status register contents, the irq output is set high up on the last falling edge of sclk of the first b yte transfer (read interrupt status register command). the irq output is held high until the last bit of the next 15 - bit transfer is shifted out (interrupt status register contents) see figure 37. if an interrupt is pending at this time, the irq output will go low again. if no interrupt is pending, the irq output will stay high. temperature measurem ent there is an on - chip temperature sensor. a temperature measurem ent can be made by setting bit 5 in the mode register. when bit 5 is set logic high in the mode register, the ade7763 initiates a temperature measurement of the next zero crossing. when the zero crossing on channel 2 is detected, the voltage output from th e temperature sensing circuit is connected to adc1 (channel 1) for digitizing. the resulting code is processed and placed in the temperature register (temp[7:0]) approximately 26 s later (24 clkin/4 cycles). if enabled in the interrupt enable register (bi t 5), the irq output will go active low when the temperature conversion is finished. the contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 lsb/c. the temperature register produces a code of 0x00 when the ambient temperature is approximately ? 25c. the temperature measurement is uncalibrated in the ade77 6 3 and might have an offset tolerance as high as 25c. analog - to - digital conversion the analog - to - digital conversion is carried out u sing two second - order - ? adcs. for simplicity, the block diagram in figure 39 shows a first - order - ? adc. the converter comprises two parts: the - ? modulator and the digital low - pass filter. 24 digital low-pass filter r c analog low-pass filter + ? v ref 1-bit dac integrator mclk/4 latched comparator .....10100101..... + ? 04481-a-040 figure 39 . first - order - ? adc a - ? modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ade7763, the sampling clock is equal to clkin/4. the 1 - bit dac in the feedback loop is driven by the serial data str eam. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and therefore the bit stream) will approach that of the input signal level. for any given input value in a sin gle sampling interval, the data from the 1 - bit adc is virtually meaningless. only when a large number of samples are averaged can a meaningful result be obtained. this averaging is carried out in the second part of the adc, the digital low - pass filter. by averaging a large number of bits from the modulator, the low - pass filter can produce 24 - bit data - words that are proportional to the input signal level. the - ? converter uses two techniques to achieve high resolution from what is essentially a 1 - bit conver sion technique. the first is oversampling. oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the band - width of interest. for example, the sampling rate in the ade7763 is clkin/4 ( 894 khz) and the band of int erest is 40 hz to 2 khz. oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest decreases see figure 40 . however, oversampling alone is not efficient enough to improve the signal - to - noise ratio (snr) in the band of interest. for example, an oversampling ratio of 4 is required just to increase the snr by 6 db (1 bit). to kee p the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at higher frequencies. in the - ? modulator, the noise is shaped by the integrator, which has a high - pass - type response for the quantization noise. the result is that most of the noise is at higher frequencies, where it can be removed by the digital low - pass filter. this noise shaping is shown in figure 40. 447 0 894 2 noise signal digital filter antialias filter (rc) sampling frequency high resolution output from digital lpf shaped noise 447 0 894 2 noise signal freq uency (khz) freq uency (khz) 04481-a-041 figure 40 . noise reduction due to oversampling and noise shaping in the analog modulator
data sheet ade7763 rev. c | page 21 of 56 antialias filter figure 39 also shows an analog low - pass filter (rc ) on the input to the modulator. this filter prevents aliasing, which is an artifact of all sampled systems. aliasing means that frequency components in the input signal to the adc that are higher than half the sampling rate of the adc appear in the sample d signal at a frequency below half the sampling rate. figure 41 illustrates the effect. frequency components (shown as arrows) above half the sampling frequency (also known as the nyquist frequency, i.e., 447 khz) a re imaged or folded back down below 447 khz. this happens with all adcs, regardless of the architecture. in the example shown, only frequencies near the sampling frequency, i.e., 894 khz, move into the band of interest for metering, i.e., 40 hz to 2 khz. t his allows the use of a very simple lpf (low - pass filter) to attenuate high frequency (near 900 khz) noise, and it prevents distortion in the band of interest. for conventional current sensors, a simple rc filter (single - pole lpf) with a corner frequency o f 10 khz produces an attenuation of approximately 40 db at 894 khz see figure 41 . the 20 db per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors; however, for a di/dt se nsor such as a rogowski coil, the sensor has a 20 db per decade gain. this neutralizes the C 20 db per decade attenuation produced by one simple lpf. therefore, when using a di/dt sensor, care should be taken to offset the 20 db per decade gain. one simple approach is to cascade two rc filters to produce the C 40 db per decade attenuation. sampling frequency image frequencies aliasing effects 0 2 447 894 freq uency (khz) 04481-a-042 figure 41 . adc and signal processing in channel 1 outline dimensions adc transfer function the following expression relates the output of the lp f in the - ? adc to the analog input signal level. both adcs in the ade7763 are designed to produce the same output code for the same input signal level. ( ) 3.0492 262,144 in out v code adc v = (1) therefore, with a full - scale signal on the input of 0.5 v and an internal reference of 2.42 v, the adc output code is nominally 165,151, or 0x2851f. the maximum code from the adc is 262,144; this is equivalent to an input signal level of 0.794 v. however, for specified performance, do not exceed the 0.5 v full - scale input sig nal level. reference circuit figure 42 shows a simplified version of the reference output circuitry. the nominal reference voltage at the ref in/out pin is 2.42 v. this is the reference voltage used for the adcs. however, channel 1 has three input range options t hat are selected by dividing down the reference value used for the adc in channel 1. the reference value used for channel 1 is divided down to ? and ? of the nominal value by using an internal resistor divider, as shown in figure 42. 60a pt a t 2.5v 1.7k? 12.5k? 12.5k? 12.5k? 12.5k? ref in/out 2.42v maximum load = 10a output impedance 6k? reference input to adc channel 1 (range select) 2.42v, 1.21v, 0.6v 04481-a-043 figure 42 . reference circuit output the ref in/out pin can be overdriven by an external source such as a 2.5 v reference. note that the nominal reference value supplied to the adcs is now 2.5 v, not 2.42 v, which increases the nominal analog input signal range by 2.5/2.42 100% = 3% or from 0.5 v to 0.5165 v. the voltage of the ade7763 reference drifts slightly with changes in temperature see table 1 for the temperature c oefficient specification (in ppm/c). the value of the temperature drift varies from part to part. because the reference is used for the adcs in both channels 1 and 2, any x% drift in the reference results in 2x% deviation in the meter accuracy. the refere nce drift that results from a temperature change is usually very small, typically much smaller than the drift of other components on a meter. however, if guaranteed temperature performance is needed, use an external voltage reference. alternatively, the me ter can be calibrated at multiple temperatures. real - time compensation can be achieved easily by using the on - chip temperature sensor. channel 1 adc figure 43 shows the adc and signal processing chain for channel 1. in waveform sam pling mode, the adc outputs a signed, twos complement, 24 - bit data - word at a maximum of 27.9 ksps (clkin/128). with the specified full - scale analog input signal of 0.5 v (or 0.25 v or 0.125 v see the analog inputs section), the adc produces an output code that is approximately between 0x28 51ec (+2,642,412d) and 0xd7 ae14 ( C 2,642,412d) see figure 43.
ade7763 data sheet rev . c | page 22 of 56 1, 2, 4, 8, 16 analog input range digital integrator* hpf adc 1 reference 2.42v, 1.21v, 0.6v v1 0v 0.5v, 0.25v, 0.125v, 62.5mv, 31.3mv, 15.6mv, channel 1 (current waveform) data range active and reactive power calculation waveform sample register current rms (irms) calculation 50hz v1p v1n pga1 v1 {gain[4:3]} {gain[2:0]} *when digital integrator is enabled, full-scale output data is attenuated depending on the signal frequency because the integrator has a ?20db/decade frequency response. when disabled, the output is not attenuated further. adc output word range 0xd7 ae14 0x0 0000 0x28 51ec 0xd7 ae14 0x00 0000 0x28 51ec channel 1 (current waveform) data range after integrator (50hz) 0xei 08c4 0x00 0000 0x1e f73c 60hz channel 1 (current waveform) data range after integrator (60hz) 0xe6 31f8 0x00 0000 0x19 ce08 04481-a-044 dt figure 43 . adc and signal processing in channel 1 channel 1 sampling the wavef orm samples may be routed to the waveform register (mode[14:13] = 1, 0) for the system master (mcu) to read. to enable waveform sampling mode, set the wsmp bit (bit 3) in the interrupt enable register to logic 1. the active and apparent power as well as th e energy calculation remain uninterrupted during waveform sampling. in waveform sampling mode, choose one of four output sample rates using bits 11 and 12 of the mode register (wavsel 1, 0). the output sample rate can be 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps see the mode register (0 x 09) section. the interrupt request output, irq , signals a new sample availability by going active low. the timing is shown in figure 44 . the 2 4 - bit wave - form samples are transferred from the ade7763 one byte (eight bits) at a time, with the most significant byte shifted out first. the 24 - bit data - word is right justified see the serial interface section. the channel 1 wav eform samples have a settling time of approximately 150 s. the interrupt request output irq stays low until the interrupt routine reads the reset status register see the interrupts section. channel 1 data (24 bits) read from waveform sign 0 irq sclk din dout 0 0 01 hex 04481-a-045 figure 44 . waveform sampling channel 1 channel 1 rms calculation the r oot mean square (rms) value of a continuous signal i (t) is defined as i rms = t dt t i t 0 2 ) ( 1 (2) for time sampling signals, the rms calculation involves squaring the signal, taking the average, and obtaining the square root: i rms = = n i i i n 1 2 ) ( 1 (3) figure 45 shows the detail of the signal processing chain for the rms calculation on channel 1. the channel 1 rms value is processed from the sa mples used in the channel 1 waveform sampling mode. the channel 1 rms value is stored in an unsigned, 24 - bit register (irms). one lsb of the channel 1 rms register is equivalent to 1 lsb of a channel 1 waveform sample. the update rate of the channel 1 rms measurement is clkin/4 . the channel 1 rms measurement has a settling time of approximately 876 ms with the integrator off and 1340 ms with the integrator on.
data sheet ade7763 rev. c | page 23 of 56 irms(t) lpf3 hpf1 channel 1 0x1c 82b3 0x00 + irmsos[11:0] irms current signal (i(t)) 2 26 2 25 sgn 2 27 2 17 2 16 2 15 04481-a-046 0x28 51ec 0x00 0xd7 ae14 24 24 figure 45 . channel 1 rms signal processing with the specified fu ll - scale analog input signal of 0.5 v, the adc produces an output code that is approximately 2,642,412d see the channel 1 adc section. the equivalent rms value of a full - scale ac signal is 1,868,467d (0x1c82b3). the current rms me asurement provided in the ade7763 is accurate to within 0.5 % for signal input between full scale and full scale/100. converting the register value to its equivalent in amps must be done externally in the microprocessor using an amps/lsb constant. to minimi ze noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings. channel 1 rms offset compensation the ade7763 incorporates a channel 1 rms offset compensa - tion register (irmsos ). this is a 12 - bit, signed register that can be used to remove offset in the channel 1 rms calculation. an offset might exist in the rms calculation due to input noises that are integrated in the dc component of v 2 (t). the offset calibra - tion e liminates t he influence of input noises from the rms measurement. one lsb of the channel 1 rms offset is equivalent to 32,768 lsb of the square of the channel 1 rms register. assuming that the maximum value from the channel 1 rms calculation is 1,868,467d with full - s cale ac inputs, then 1 lsb of the channel 1 rms offset represents 0.46% of the measurement error at C 60 db down of full scale. i rms = 32768 2 + irmsos irms 0 (4) where irms 0 is the rms measurement without offset correction. to measure the offset of the rm s measurement, two data points are needed from nonzero input values, for example, the base current , i b , and i max /100 . the offset can be calculated from these measurements. note that for correct operation , only positive values should be written to the irmso s register. channel 2 adc channel 2 sampling to enable waveform sampling mode, set the wsmp bit (bit 3) in the interrupt enable register to logic 1 . in channel 2 waveform sampling mode (mode[14:13] = 1, 1 and wsmp = 1) , the adc output code scaling for cha nnel 2 is not the same as it is for channel 1. the channel 2 waveform sample is a 16 - bit word and sign extended to 24 bits. the c hannel 2 waveform samples have a settling time of approximately 1.23 ms. for normal operation, the differential voltage signal b etween v2p and v2n should not exceed 0.5 v. with maximum voltage input (0.5 v at pga gain of 1), the output from the adc swings between 0x2852 and 0xd7ae (10,322d). however, before being passed to the waveform register, the adc output is passed through a single - pole, low - pass filter with a cutoff frequency of 140 hz. the plots in figure 46 show the magnitude and phase response of this filter. frequency (hz) 0 10 1 10 2 10 3 phase (degrees) ?20 ?10 ?40 ?50 ?60 ?30 ?70 ?80 ?90 0 ?18 gain (db) 60hz, ?0.73db 50hz, ?0.52db 60hz, ?23.2 50hz, ?19.7 ?8 ?10 ?14 ?12 ?16 ?2 ?4 ?6 04481-a-047 figure 46 . magnitude and phase response of lpf1 the lpf1 has the effect of attenuating the signal. for example, if the line frequency is 60 hz, the signal at the output of lpf1 will be attenuated by about 8%. | h ( f )| = 2 hz 140 hz 60 1 1 ? ? ? ? ? ? ? ? + = 0.919 = ? 0.73 db (5) note lpf1 does not affect the active power calculation. the signal processing chain in channel 2 is illustrated in figure 47.
ade7763 data sheet rev . c | page 24 of 56 v1 adc 2 0v analog input range 0.5v, 0.25v, 0.125v, 62.5mv, 31.25mv reference lpf1 a c t i v e a n d r e a c t i v e e n e r g y c a l c u l a t i o n v r m s c a l c u l a t i o n a n d w a v e f o r m s a m p l i n g ( p e a k / s a g / z x ) pga2 1, 2, 4, 8, 16 {gain[7:5]} v2p v2n v2 2.42v 0x2852 0x2581 0xdae8 0xd7ae 0x0000 lpf output word range 04481-a-048 figure 47 . adc and signal processing in channel 2 04481-a-049 vrms[23:0] lpf3 lpf1 channel 2 |x| 0x17d338 0x00 + + vrmos[11:0] voltage signal (v(t)) 2 9 sgn 2 8 2 2 2 1 2 0 0x2518 0x0 0xdae8 figure 48 . channel 2 rms signal processing channel 2 has only one analog input range (0.5 v differential). like channel 1, channel 2 has a pga with gain selections of 1, 2, 4, 8, and 16. for energy measurement, the output o f the adc is passed directly to the multiplier and is not filtered. an hpf is not required to remove any dc offset; it is only required that the offset is removed from one channel to eliminate errors caused by offsets in the power calculation. in waveform sampling mode, one of four output sample rates can be chosen by using bits 11 and 12 of the mode register. the available output sample rates are 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps see the mode register (0 x 09) section. the inte rrupt request output irq indicates that a sample is available by going active low. the timing is the same as that for channel 1, as shown in figure 44. channel 2 rms calculation figure 48 shows the details of the signal processing chain for the rms estimation on channel 2. this channel 2 rms estimation is done in the ade7763 using the mean absolute value calculation , as shown in figure 48. the channel 2 rms value is processed from the samples used in the channel 2 waveform sampling mode. the rms value is slightly attenuated due to lpf1. the channel 2 rms value is stored in the unsigned, 24 - bit vrms register. the update rate of the channel 2 rms measure ment is clkin/4 . the c hannel 2 rms measurement has a settling time of approximately 670 ms. with the specified full - scale ac analog input signal of 0.5 v, the output from lpf1 swings between 0x2518 and 0xdae8 at 60 hz see the channe l 2 adc section. the equivalent rms value of this full - scale ac signal is approximately 1,561,400 (0x17 d338) in the vrms register. the voltage rms measure - ment provided in the ade7763 is accurate to within 0.5% for signal input between full scale and f ull scale/20. the conversion from the register value to volts must be done externally in the microprocessor using a volts/lsb constant. because the low - pass filter used for calculating the rms value is imperfect, there is some ripple noise from 2 term pre sent in the rms measurement. to minimize the effect of noise in the reading, synchronize the rms reading with the zero crossings of the voltage input. channel 2 rms offset compensation the ade7763 incorporates a channel 2 rms offset compensation register ( vrmsos). this is a 12 - bit, signed register that can be used to remove offset in the channel 2 rms calculation. an offset could exist in the rms calculation due to input noises and dc offset in the input samples. one lsb of the channel 2 rms offset is equiv alent to 1 lsb of the rms register. assuming that the maximum value of the channel 2 rms calculation is 1,561,400d with full - scale ac inputs, then 1 lsb of the channel 2 rms offset represents 0.064% of measurement error at C 60 db down of full scale. vrms = vrms 0 + vrmsos (6) where v rms 0 is the rms measurement without offset correction. the voltage rms offset compensation should be done by testing the rms results at two nonzero input levels. one measurement can be done close to full scale and the other at a pproximately full scale/10. the voltage offset compensation can be derived from these measurements. if the voltage rms offset register does not have enough range, the ch2os register can also be used. phase compensation when the hpf is disabled, the phase error between channel 1 and channel 2 is 0 from dc to 3.5 khz. when hpf is enabled, channel 1 has the phase response illustrated in figure 50 and
data sheet ade7763 rev. c | page 25 of 56 figure 51. figure 52 shows the magn itude response of the filter. as seen from the plots, the phase response is almost 0 from 45 hz to 1 khz, which is all that is required in typical energy measurement applications. however, despite being internally phase - compensated, the ade7763 must work w ith transducers, which could have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not uncommon for a current transformer (ct). phase errors can vary from part to part and must be corrected in order to perform accurate power calculation s. the errors associated with phase mismatch are particularly noticeable at low power factors. the ade7763 provides a means of digitally calibrating these small phase errors by allowing a short time delay or time advance to be introduced into the signal pr ocessing chain to compensate for these errors. because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1 to 0.5. correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. the phase calibration register (phcal[5:0]) is a twos comple - ment, signed, single - byte register that has values ranging from 0x21 ( C 31d) to 0x1f (+31d). the register is centered at 0dh, so that writing 0dh to the register produces 0 delay. by changing the phcal register, the time delay in the channel 2 signal path can change from C 102.12 s to +39.96 s (clkin = 3.579545 mhz). one lsb is equivalent to 2.22 s ( clkin/8 ) time delay or advance. a line frequency of 60 hz gives a phase resolution of 0.048 at the fundamental (i.e., 360 2.22 s 60 hz). figure 49 illustrates how the phase compensation is used to remove a 0.1 phase lead in channel 1 due to the external transducer. to cancel the lead ( 0.1) in channel 1, a phase lead must also be introduced into channel 2. the resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.048. the phase lead is achieved by introducing a time advance in channel 2. a time a dvance of 4.44 s is made by writing ?2 (0x0b) to the time delay block, thus reducing the amount of time delay by 4.44 s, or equivalently, a phase lead of approximately 0.1 at line frequency of 60 hz. 0x0b represents C 2 because the register is centered w ith 0 at 0dh. 1 1 0 1 0 0 1 5 0 pga1 v1p v1n v1 adc 1 hpf 24 pga2 v2p v2n v2 adc 2 delay block 2.22 s/lsb 24 lpf2 v2 v1 60hz 0.1 v1 v2 channel 2 delay reduced by 4.44 s (0.1 lead at 60hz) 0x0b in phcal [5.0] phcal[5:0] ? 102.12 s to +39.96 s 60hz 04481-a-050 figure 49 . phase calibration frequency (hz) phase (degrees) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ? 0.1 10 2 10 3 10 4 04481-a-051 figure 50 . combined phase response of hpf and phase compensation (10 hz to 1 khz) frequency (hz) 0.20 40 phase (degrees) 0.18 0.16 0.14 0.12 0.10 0.08 0 0.02 0.04 0.06 45 50 55 60 65 70 04481-a-052 figure 51 . combined phase response of hpf and phase compensation (40 hz to 70 hz) frequency (hz) 0.4 err or (%) 54 56 58 60 62 64 66 0.3 0.2 0.1 0.0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 04481-a-053 figure 52 . combined gain response of hpf and phase compensation active power calcula tion power is defined as the rate of energy flow from the source to the load. it is defined as the product o f the voltage and current wave forms. the resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at any given time. the unit of power is the watt or joules/s. equation 9 gives an expression for the instantaneous power signal in an ac system.
ade7763 data sheet rev. c | page 26 of 56 )sin(2)( tvtv ?? (7) )sin(2)( titi ?? (8) where: v is the rms voltage. i is the rms current. )()()( titvtp ?? )2cos( )( tvivitp ??? (9) the average power over an integral number of line cycles (n) is given by the expression in equation 10. ? ? ? nt vidttp nt p 0 )( 1 (10) where: t is the line cycle period. p is the active or real power. note that the active power is equal to the dc component of the instantaneous power signal p( t ) in equation 8, i.e., vi . this is the relationship used to calculate active power in the ade7763. the instantaneous power signal p( t ) is generated by multiplying the current and voltage signals. the dc component of the instan- taneous power signal is then extracted by lpf2 (low-pass filter) to obtain the active power information. this process is illustrated in figure 53. instantaneous power signal p(t) = v ? i-v ? i ? cos(2 ? t) active real power signal = v ? i 0x19 999a vi 0xc cccd 0x0 0000 04481-a-054 current i(t) = 2 ? i ? sin( ? t) voltage v(t) = 2 ? v ? sin( ? t) figure 53. active power calculation because lpf2 does not have an ideal brick wall frequency response (see figure 54), the active power signal has some ripple due to the instantaneous power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energysee the energy calculation section. frequency (hz) ?24 1 db ?20 3 10 30 100 ?12 ?16 ?8 ?4 0 04481-a-055 figure 54. frequency response of lpf2
data sheet ade7763 rev. c | page 27 of 56 apos[15:0] wgain[11:0] wdiv[7:0] lpf2 current channel voltage channel output lpf2 time (nt) 4 clkin t active power signal + + aenergy[23:0] outputs from the lpf2 are accumulated (integrated) in the internal active energy register upper 24 bits are accessible through aenergy[23:0] register 23 0 48 0 waveform register values 04481-a-056 % figure 55. active energy calculation figure 55 shows the signal processing chain for the active power calculation. the active power is calculated by low-pass filtering the instantaneous power signal. note that when reading the waveform samples from the output of lpf2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (wgain[11:0]). the gain is adjusted by writing a twos complement 12-bit word to the watt gain register. equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? 12 2 1 wgain power active wgain output (11) for example, when 0x7ff is written to the watt gain register, the power output is scaled up by 50%. 0x7ff = 2047d, 2047/2 12 = 0.5. similarly, 0x800 = C2048d (signed twos complement) and power output is scaled by C50%. each lsb scales the power output by 0.0244%. figure 56 shows the maximum code (hexadecimal) output range for the active power signal (lpf2). note that the output range changes depending on the contents of the watt gain register. the minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7ff to the watt gain register. this can be used to calibrate the active power (or energy) calculation. 0x1 3333 0xcccd 0x6666 0xf 999a 0xf 3333 0xe cccd 0x0 0000 active power output positive power negative power 0x000 0x7ff 0x800 {wgain[11:0]} active power calibration range 04481-a-057 figure 56. active power calculation output range energy calculation as stated earlier, power is defined as the rate of energy flow. this relationship is expressed mathematically in equation 12. dt de p ? (12) where: p is power. e is energy. conversely, energy is given as the integral of power. ? ? pdte (13)
ade7763 data sheet rev. c | page 28 of 56 for waveform accumulation 1 24 24 lpf2 v i 0x1 9999 0x19 999a 0x00 0000 instantaneous power signal ? p(t) for wavef0rm sampling 32 0xc cccd current signal ? i(t) hpf voltage signal? v(t) multiplier + + apos[15:0] 2 6 sgn 2 5 2 -6 2 -7 2 -8 04481-a-058 wgain[11:0] figure 57. active power signal processing the ade7763 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal unreadable 49-bit energy register. the active energy register (aenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 14 expresses this relationship. 0 1 () ( ) t n e p t dt lim p nt t ? ? ? ?? ?? ? ?? ? ? ? ? (14) where: n is the discrete time sample number. t is the sample period. the discrete time sample period ( t ) for the accumulation register is 1.1 s (4/clkin). in addition to calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. figure 57 shows this discrete time integration, or accumulation. the active power signal in the waveform register is continuously added to the internal active energy register. this addition is a signed addition; therefore, negative energy is subtracted from the active energy contents. the exception to this is when poam is selected in the mode[15:0] register, in which case only positive energy contributes to the active energy accumulation see the positive-only accumulation mode section. the output of the multiplier is divided by wdiv. if the value in the wdiv register is equal to 0, then the internal active energy register is divided by 1. wdiv is an 8-bit, unsigned register. after dividing by wdiv, the active energy is accumulated in a 49-bit internal energy accumulation register. the upper 24 bits of this register are accessible through a read to the active energy register (aenergy[23:0]). a read to the raenergy register returns the content of the aenergy register, and the upper 24 bits of the internal register are cleared. as shown in figure 57, the active power signal is accumulated in an internal 49-bit, signed register. the active power signal can be read from the waveform register by setting mode[14:13] = 0, 0 and setting the wsmp bit (bit 3) in the interrupt enable register to 1. like channel 1 and channel 2 waveform sampling modes, the waveform data is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 kspssee figure 44. the active power waveform sampling signal has a settling time of approximately 2 ms. figure 58 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. the three curves illustrate the minimum time for the energy register to roll over when the active power gain register contents are 0x7ff, 0x000, and 0x800. the watt gain register is used to carry out power calibration. as shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7ff. 0x00 0000 0x7f ffff 0x3f ffff 0x40 0000 0x80 0000 aenergy[23:0] 6.2 48 12.5 time (minutes) wgain = 0x7ff wgain = 0x000 wgain = 0x800 04481-a-059 figure 58. energy register rollov er time for full-scale power (minimum and maximum power gain) note that the energy register contents roll over to full-scale negative (0x80 0000) and continue increasing in value when the power or energy flow is positivesee figure 58. conversely, if the power was negative, the energy register would underflow to full-scale positive (0x7f ffff) and continue decreasing in value. by using the interrupt enable register, the ade7763 can be configured to issue an interrupt ( irq ) when the active energy register is more than half full (positive or negative), or when an overflow or underflow occurs.
data sheet ade7763 rev. c | page 29 of 56 integration time under steady load as mentioned in the last section, the discrete time sample period ( t ) for the acc umulation register is 1.1 s ( 4/clkin ). with full - scale sinusoidal signals on the analog inputs and the wgain register set to 0x000, the average word value from each lpf2 is 0xc cccd see figure 53 . the maximum positive value that c an be stored in the internal 49 - bit register before it overflows is 2 48 , or 0xffff ffff ffff. the integration time under these conditions with wdiv = 0 is calculated as follows: time = min 26 . 6 s 8 . 375 s 12 . 1 cccd 0xc ffff ffff 0xffff = = (15) when wdiv is set to a value other than 0, the integration time varies, as shown in equation 16. time = time wdiv = 0 wdiv (16) power offset calibra tion the ade7763 incorporates an active power offset register (apos [ 15:0]). this is a signed , twos complement , 16- bit register that can be used to remove offsets in the active power calculation see figure 57 . an offset could exist in the power calculation due to crosstalk between channels on the pcb or in the ic itself. the 256 lsbs (apos = 0x0100) written to the active power offset register are equivalent to 1 lsb in the waveform sample register. assuming the average value output from lpf2 is 0xc cccd (838,861d) when inputs on channels 1 and 2 are both at full scale. at ?60 db down on chann el 1 (1/1000 of the channel 1 full - scale input), the average word value output from lpf2 is 838.861 (838,861/1,000). one lsb in the lpf2 output has a measurement error of 1/838.861 100% = 0.119% of the average value. the active power offset register has a resolution equal to 1/256 lsb of the waveform register; therefore, the power offset correction resolution is 0.00047%/lsb (0.119%/256) at C 60 db. energy - to - frequency conversion the ade7763 provides energy - to - frequency conversion for calibration purposes. after initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. one convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to t he energy or active power under steady load conditions. this output frequency can provide a simple, single - wire, optically isolated interface to external calibration equip - ment. figure 59 illustrates the energy - to - frequency convers ion. cfnum[11:0] cf 11 0 cfden[11:0] 11 0 aenergy[48:0] 48 0 04481-a-060 % dfc figure 59 . energy - to- frequency conversion a digital - to - frequency converter (dfc) is used to generate the cf pulsed output. the dfc generates a pulse each time 1 lsb in the active energy register is accumulated. an output pul se is generated when (cfden + 1)/(cfnum + 1) number of pulses are generated at the dfc output. under steady load conditions, the output frequency is proportional to the active power. the maximum output frequency, with ac input signals at full scale, cfnum = 0x00, and cfden = 0x00, is approximately 23 khz. there are two unsigned, 12 - bit registers, cfnum[11:0] and cfden[11:0], that can be used to set the cf frequency to a wide range of values. these frequency - scaling registers are 12 - bit registers that can sc ale the output frequency by 1/2 12 to 1 with a step of 1/2 12 . if the value 0 is written to any of these registers, the value 1 will be applied to the register. the ratio (cfnum + 1)/(cfden + 1) should be smaller than 1 to ensure proper operation. if the rat io of the registers (cfnum + 1)/(cfden + 1) is greater than 1, the register values will be adjusted to a ratio (cfnum + 1)/ (cfden + 1) of 1. for example, if the output frequency is 1.562 khz while the contents of cfden are 0 (0x000), then the output frequ ency can be set to 6.1 hz by writing 0xff to the cfden register. when cfnum and cfden are both set to one, the cf pulse width is fixed at 16 clkin/4 clock cycles, approximately 18 s with a clkin of 3.579545 mhz. if the cf pulse output is longer than 180 m s for an active energy frequency of less than 5.56 hz, the pulse width is fixed at 90 ms. otherwise, the pulse width is 50% of the duty cycle. the output frequency has a slight ripple at a frequency equal to twice the line frequency. this is due to imperf ect filtering of the instantaneous power signal to generate the active power signal see the active power calculation section. equation 8 gives an expression for the instantaneous power signal. this is filtered by lpf2, which has a magnitude response given by equation 17. 2 9 . 8 1 1 ) ( 2 f f h + = (17)
ade7763 data sheet rev. c | page 30 of 56 the active power signal (output of lpf2) can be rewritten as )4cos( 9.8 2 1 )( 2 tf f vi vitp l l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? (18) where f l is the line frequency, for example, 60 hz. from equation 13, )4sin( 9.8 2 14 )( 2 tf f f vi vitte l l l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? (19) note that in equation 19 there is a small ripple in the energy calculation due to a sin(2t) component. this is shown graphi- cally in figure 60. the active energy calculation is represented by the dashed, straight line and is equal to v i t. the sinu- soidal ripple in the active energy calculation is also shown. because the average value of a sinusoid is 0, the ripple does not contribute to the energy calculation over time. however, the ripple might be observed in the frequency output, especially at higher output frequencies. the ripple becomes larger as a percentage of the frequency at larger loads and higher output frequencies. this occurs because the integration or averaging time in the energy-to-frequency conversion process is shorter at higher output frequencies. consequently, some of the sinusoidal ripple in the energy signal is observable in the frequency output. choosing a lower output frequency at cf for calibration can significantly reduce the ripple. also, averaging the output frequency by using a longer gate time for the counter achieves the same results. vi ? sin(4 ??? f l ? t) 4 ??? f l (1+2 ? f l /8. 9hz ) e(t) t vlt 04481-0-061 figure 60. output frequency ripple 04481-a-062 wdiv[7:0] apos[15:0] wgain[11:0] lpf1 + + laenergy[23:0] accumulate active energy in internal register and update the laenergy register at the end of linecyc line cycles output from lpf2 from channel 2 adc 23 0 linecyc[15:0] 48 0 % zero crossing detection calibration control figure 61. energy calculation line cycle energy accumulation mode
data sheet ade7763 rev. c | page 31 of 56 line cycle energy accumulation mode in line cycle energy accumulation mode, the energy accumu- lation of the ade7763 can be synchronized to the channel 2 zero crossing so that active energy accumulates over an integral number of half line cycles. the advantage of summing the active energy over an integral number of line cycles is that the sinusoidal component in the active energy is reduced to 0. this eliminates ripple in the energy calculation. energy is calculated more accurately and in a shorter time because the integration period is shortened. by using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. the ade7763 is placed in line cycle energy accumulation mode by setting bit 7 (cycmode) in the mode register. in line cycle energy accumulation mode, the ade7763 accumulates the active power signal in the laenergy register (address 0x04) for an integral number of line cycles, as shown in figure 61. the number of half line cycles is specified in the linecyc register (address 0x1c). the ade7763 can accumulate active power for up to 65,535 half line cycles. because the active power is integrated on an integral number of line cycles, the cycend flag in the interrupt status register is set (bit 2) at the end of a line cycle energy accumulation cycle. if the cycend enable bit in the interrupt enable register is enabled, the irq output also will go active low. therefore, the irq line can also be used to signal the completion of the line cycle energy accumulation. another calibration cycle can start as long as the cycmode bit in the mode register is set. from equations 13 and 18, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? nt nt dttf f vi dtvite 0 2 0 )2cos( 9.8 1 )( ? (20) where: n is an integer. t is the line cycle period. since the sinusoidal component is integrated over an integral number of line cycles, its value is always 0. therefore, ? ?? nt vidte 0 0 (21) ?? et vint ? (22) note that in this mode, the 16-bit linecyc register can hold a maximum value of 65,535. in other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration of 65,535 half line cycles. at 60 hz line frequency, this translates to a total duration of 65,535/ 120 hz = 546 seconds. positive-only accumulation mode in positive-only accumulation mode, the active energy accumulation is only done for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in figure 62. the cf pulse also reflects this accumulation method when in this mode. positive-only accumulation mode is activated by setting the msb of the mode register (mode[15]) and effects only the active power. the default setting for this mode is off. transitions in the direction of power flow, going from negative to positive or positive to negative, set the irq pin to active low if the ppos and pneg bits are set in the interrupt enable register. the corresponding ppos and pneg bits in the interrupt status register show which transition has occurredsee the register descriptions in table 9. pneg ppos ppos interrupt status registers ppos pneg pneg irq no-load threshold active power no-load threshold a ctive energ y 04481-a-063 figure 62. energy accumulation in positive-only accumulation mode no-load threshold the ade7763 includes a no-load threshold feature on the active energy that eliminates any creep effects in the meter. this is accomplished because energy does not accumulate if the multiplier output is below the no-load threshold. this threshold is 0.001% of the full-scale output frequency of the multiplier. compare this value to the iec1036 specification, which states that the meter must start up with a load equal to or less than 0.4% i b . this standard translates to 0.0167% of the full-scale output frequency of the multiplier.
ade7763 data sheet rev. c | page 32 of 56 apparent power calculation the apparent power is the maximum power that can be delivered to a load. v rms and i rms are the effective voltage and current delivered to the load; the apparent power (ap) is defined as v rms i rms . the angle between the active power and the apparent power generally represents the phase shift due to nonresistive loads. for single-phase applications, represents the angle between the voltage and the current signalssee figure 63. equation 24 gives an expression of the instantaneous power signal in an ac system with a phase shift. reactive power apparent power active power 04481-a-064 ? figure 63. power triangle () 2 sin( ) rms vt v t ? ? () 2 sin( ) rms it i t ? ? ?? (23) )()()( titvtp ?? )2cos( )cos( )( ?? ? ? ? ? t iv ivtp rmsrms rmsrms (24) the apparent power is defined as v rms i rms . this expression is independent from the phase angle between the current and the voltage. figure 64 illustrates the signal processing in each phase for the calculation of the apparent power in the ade7763. v rms i rms 0xa d055 apparent power signal (p) current rms signal ? i(t) voltage rms signal? v(t) multiplier 04481-a-065 0x00 0x1c 82b3 0x00 0x17 d338 vagain figure 64. apparent power signal processing the gain of the apparent energy can be adjusted by using the multiplier and vagain register (vagain[11:0]). the gain is adjusted by writing a twos complement, 12-bit word to the vagain register. equation 25 shows how the gain adjustment is related to the contents of the vagain register. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? 12 2 1 vagain power apparent in outputvaga (25) for example, when 0x7ff is written to the vagain register, the power output is scaled up by 50%. 0x7ff = 2047d, 2047/2 12 = 0.5. similarly, 0x800 = C2047d (signed, twos complement) and power output is scaled by C50%. each lsb represents 0.0244% of the power output. the apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ade7763. figure 65 shows the maximum code (hexadecimal) output range of the apparent power signal. note that the output range changes depending on the contents of the apparent power gain registers. the minimum output range is given when the apparent power gain register content is equal to 0x800; the maximum range is given by writing 0x7ff to the apparent power gain register. this can be used to calibrate the apparent power (or energy) calculation in the ade7763. 0x10 3880 0xa d055 0x5 682b 0x0 0000 0x000 0x7ff 0x800 {vagain[11:0]} apparent power 100% fs apparent power 150% fs apparent power 50% fs apparent power calibration range, voltage and current channel inputs: 0.5v/gain 04481-a-066 figure 65. apparent power calculation output range apparent power o ffset calibration each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms valuesee the channel 1 rms calculation and channel 2 rms calculation sections. the channel 1 and channel 2 rms values are then multiplied together in the apparent power signal processing. because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. the offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.
data sheet ade7763 rev. c | page 33 of 56 apparent energy calculation the apparent energy is given as the integral of the apparent power. ? ? dttpower apparent energy apparent )( (26) the ade7763 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 49-bit register. the apparent energy register (vaenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 29 expresses this relationship. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 )( n t tntpower apparent lim energy apparent (27) where: n is the discrete number of time samples. t is the time sample period. the discrete time sample period ( t ) for the accumulation register is 1.1 s (4/clkin). figure 66 shows this discrete time integration or accumulation. the apparent power signal is continuously added to the internal register. this addition is a signed addition, even if the apparent energy always remains positive in theory. the 49 bits of the internal register are divided by vadiv. if the value in the vadiv register is 0, then the internal active energy register is divided by 1. vadiv is an 8-bit, unsigned register. the upper 24 bits are then written in the 24-bit apparent energy register (vaenergy[23:0]). rvaenergy register (24 bits long) is provided to read the apparent energy. this register is reset to 0 after a read operation. figure 67 shows this apparent energy accumulation for full- scale signals (sinusoidal) on the analog inputs. the three curves illustrate the minimum time for the energy register to roll over when the vagain registers content is equal to 0x7ff, 0x000, and 0x800. the vagain register is used to carry out an apparent power calibration. as shown in the figure, the fastest integration time occurs when the vagain register is set to maximum full scale, i.e., 0x7ff. vadiv apparent power + + vaenergy[23:0] apparent power is accumulated (integrated) in the apparent energy register 23 0 48 0 48 0 04481-a-067 % time (nt) t active power signal = p figure 66. apparent energy calculation 0 xff ffff 0x80 0000 0x40 0000 0x20 0000 0x00 0000 vaenergy[23:0] 6.26 12.52 18.78 25.04 time (minutes) vagain = 0x7ff vagain = 0x000 vagain = 0x800 04481-a-068 figure 67. energy register rollov er time for full-scale power (maximum and minimum power gain) note that the apparent energy register is unsignedsee figure 67. by using the interrupt enable register, the ade7763 can be configured to issue an interrupt ( irq ) when the apparent energy register is more than half full or when an overflow occurs. the half full interrupt for the unsigned apparent energy register is based on 24 bits, as opposed to 23 bits for the signed active energy register.
ade7763 data sheet rev . c | page 34 of 56 integration times under steady load as mentioned in the last section, the discrete time sample period ( t ) for the accumulation register is 1.1 s ( 4/clkin ). with full - scale sinusoidal signals on the analog inputs and the vagain register set to 0x000, the average word value from the app arent power stage is 0xa d055. the maximum value that can be stored in the apparent energy register before it overflows is 2 24 or 0xff ffff. the average word value is added to the internal register, which can store 2 48 or 0xffff ffff ffff before it overflo ws. therefore, the integration time under these conditions with vadiv = 0 is calculated as follows: min 52 . 12 888 2 . 1 0xad055 ffff ffff 0xffff = = = s s time (28) when vadiv is set to a value other than 0, the integration time varies, as shown in equation 29. time = time wdiv = 0 vadiv (2 9) line apparent energy accumulation the ade7763 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. by using the on - chip zero - crossing detection, the ade7763 accumulates the apparent power signal in the lvaenergy register for an integral number of half cycles, as shown in figure 68 . the line apparent energy accumulation mode is always active. the number of half line cycles is specified in the linecyc register, which is an unsigne d, 16 - bit register. the ade7763 can accumulate apparent power for up to 65,535 combined half cycles. because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be easily comp ared. the active and apparent energies are calculated more accurately because of this precise timing control. at the end of an energy calibration cycle, the cycend flag in the interrupt status register is set. if the cycend mask bit in the interrupt mask r egister is enabled, the irq output also will go active low. thus, the irq line can also be used to signal the end of a calibration. the line apparent energy accumulation uses the same signal path as the apparent energy a ccumulation. the lsb size of these two registers is equivalent. vadiv[7:0] lpf1 + + lvaenergy[23:0] lvaenergy register is updated every linecyc zero crossings with the total apparent energy during that duration apparent power from channel 2 adc 23 0 linecyc[15:0] 48 0 04481-a-069 % zero-crossing detection calibration control figure 68 . apparent energy calibration
data sheet ade7763 rev. c | page 35 of 56 energ ies scaling the ade7763 provides measurements of active and apparent energ ies . these measurements do not have the s ame scaling and therefore cannot be compared directly to each other. table 7 . energies scaling pf = 1 pf = 0.707 pf = 0 integrator o n at 50 hz active wh wh 0.707 0 apparent wh 0.848 wh 0.848 wh 0.848 integrator o ff at 5 0 hz active wh wh 0.707 0 apparent wh 0.848 wh 0.848 wh 0.848 integrator o n at 60 hz active wh wh 0.707 0 apparent wh 0.827 wh 0.827 wh 0.827 integrator o ff at 60 hz active wh wh 0.707 0 apparent wh 0.827 wh 0.827 wh 0.827 calibrating an energ y meter the ade7763 provides gain and offset compensation for active and apparent energy calibration. its phase compensation corrects phase error in active and apparent energy. if a shunt is used, offset and phase calibration may not b e required. a reference meter or an accurate source can be used to calibrate the ade7763. when using a reference meter, the ade7763 calibration output frequency, cf, is adjusted to match the frequency output of the reference meter. a pulse output is only provided for the active energy measurement in the ade7763 . if a reference meter is used to calibrate the va, then additional code must be written in a microprocessor to produce a pulsed output for this quantity. otherwise, va calibration requires an accur ate source. the ade7763 provides a line cycle accumulation mode for calibration using an accurate source. in this method, the active energy accumulation rate is adjusted to produce a desired cf frequency. the benefit of using this mode is that the effect o f the ripple noise on the active energy is eliminated. up to 65,535 half line cycles can be accumulated, therefore providing a stable energy value to average. the accumulation time is calculated from the line cycle period, measured by the period register, and the number of half line cycles in the accumulation, fixed by the linecyc register. current and voltage rms offset calibration removes apparent energy offset. a gain calibration is also provided for apparent energy. figure 70 shows an optimized calibration flow for active energy, rms, and apparent energy. active and apparent energy gain calibrations can take place concurrently, with a read of the accumulated apparent energy register following that of the accumula ted active energy register. figure 69 shows the calibration flow for the active energy portion of the ade7763. watt gain calibration watt offset calibration phase calibration 04481-a-083 figure 69 . active energy calibration watt/va gain calibration watt offset calibration rms calibration phase calibration 04481-a-084 figure 70 . apparent and active energy calibration
ade7763 data sheet rev . c | page 36 of 56 watt gain the first step of calibrating the gain is to define the line voltage, the base current , and the maximum current for the meter. a meter constant, such as 3200 imp/kwh or 3.2 imp/wh , needs to be determi ned for cf. note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example . the expected cf in hz is cf expected (hz) = ) cos( s/h 3600 ) w ( ) imp/wh ( ? load ant meterconst (30 ) w here : ? is the angle betwe en i and v . cos ) ( ? is the power factor. the ratio of active energy lsbs per cf pulse is adjusted using the cfnum, cfden, and wdiv registers. cf expected = ) 1 ( ) 1 ( (s) + + cfden cfnum wdiv ontime accumulati laenergy (31 ) the relationship between w att - hours accumulated and the quantity read from aenergy can be determined from the amount of active energy accumulated over time with a given load: s/h 3600 ) ( (w) lsb wh = laenergy s time on accumulati load (3 2 ) where accumulation time can be determined from the value in the line period and the number of half li ne cycles fixed in the linecyc register. accumulation time (s) = 2 ) ( s period line linecyc ib (3 3 ) the line period can be determined from the period register: line period (s) = period clkin 8 (3 4 ) the aenergy wh/lsb ratio can also be expressed i n terms of the meter constant: (imp/wh) ) 1 ( ) 1 ( lsb wh ant meterconst wdiv cfden cfnum + + = (3 5 ) in a meter design, w d i v, c f n u m , and cfden should be kept constant across all meters to ensure that the wh/lsb constant is maintained. leaving wdiv at its default value of 0 ensures maximum resolu tion. t he wdiv register is not included in the cf signal chain , so it does not affect the frequency pulse output . the wgain register is used to finely calibrate each meter. cali - brating the wgain register changes both cf and aenergy for a given load condi tion. aenergy expected = aenergy nominal ? ? ? ? ? ? + 12 2 1 wgain ( 36) cf expected (hz) = cf nominal ? ? ? ? ? ? + + + 12 2 1 ) 1 ( ) 1 ( wgain cfden cfnum ( 37) when calibrating with a reference meter, wgain is adjusted until cf matches the reference meter pulse output. if an accurate source is used to calibrate, wgain will be modified until the active energy accumulation rate yields the expected cf pulse rate. the steps of designing and calibrating the active energy portion of a meter with either a reference meter or an accurate sourc e are outlined in the following examples. the specifications for this example are meter constant: meterconstant (imp/wh) = 3.2 base current: i b = 10 a maximum current: i max = 60 a line voltage: v nominal = 220 v line frequency: f l = 50 hz the first ste p in calibration with either a reference meter or an accurate source is to calculate the cf denominator, cfden. this is done by comparing the expected cf pulse output to the nominal cf output with the default cfden = 0x3f and cfnum = 0x3f when the base cur rent is applied. the expected cf output for this meter with the base current applied is 1.9556 hz using equation 30. cf ib ( expected ) (hz) = hz 9556 . 1 ) cos( s/h 3600 v 220 a 10 imp/wh 200 . 3 = ? alternatively, cf expected can be measured from a reference meter pulse output. cf expected (h z) = cf ref (38 ) the maximum cf frequency measured without any frequency division and with ac inputs at full scale is 23 khz. for this example, the nominal cf with the test current, i b , applied is 958 hz . in this example t he line vol tage and maximum current scale half of their respective analog input ranges. the line voltage and maximum current should not be fixed at the maximum analog inputs to account for occurrences such as spikes on the line. cf nominal (hz) = max i i 2 1 2 1 khz 23 (39) cf ib ( nominal ) (hz) = hz 958 60 10 2 1 2 1 khz 23 = the nominal cf on a sample set of meters should be measured using the default cfden, cfnum, and wdiv to ensure that the best cfden is chosen for the design. with the cfnum register set to 0, cfden is calculated to be 489 for the example meter:
data sheet ade7763 rev. c | page 37 of 56 cfden = 1 ) ( ) ( ? ? ? ? ? ? ? ? ? expected ib nominal ib cf cf int (4 0 ) cfden = 489 ) 1 490 ( 1 9556 . 1 958 = ? = ? ? ? ? ? ? ? int this value for cfden should be loaded into each meter before calibration. the wgain register can then be used to finely calibrate the cf output. the following sections ex plain how to calibrate a meter based on ade7763 when using a reference meter or an accurate source. calibrating watt gain using a reference meter example the cfden and cfnum values for the design should be written to their respective registers before begin ning the calibration steps shown in figure 71 . when using a reference meter, the percent error in cf is measured by comparing the cf output of the ade7763 meter with the pulse output of the reference meter, using the same test cond itions for both meters. equation 41 defines the percent error with respect to the pulse outputs of both meters (using the base current, i b ): % error cf ( ib ) = 100 ) ( ) ( ? ib ref ib ref ib cf cf cf (4 1 ) calculate cfden value for design write cfden value to cfden register addr. 0x15 = cfden write wgain value to the wgain register: addr. 0x12 measure the % error between the cf output and the reference meter output set i test = i b , v test = v nom , pf = 1 04481-a-085 calculate wgain. see equation 42. figure 71 . calibrating watt gain u sing a re ference meter for this example: meter constant: meterconstant (imp/wh) = 3.2 cf numerator: cfnum = 0 cf denominator: cfden = 489 %e rror measu red at base current: % error cf ( ib ) = ? 3.07% one lsb change in wgain changes the active energy register s an d cf by 0.0244%. wgain is a signed, twos complement register and can correct up to a 50% error. assuming a ? 3.07% error, wgain is 126: wgain = int ? ? ? ? ? ? ? ? ? % 0244 . 0 % ) ( ib cf error (4 2 ) wgain = int 126 % 0244 . 0 % 07 . 3 = ? ? ? ? ? ? ? ? when cf is calibrated, the aenergy register has the same wh/lsb constant from meter to meter if the meter constant, w d i v, and the cf num/cfden ratio remain the same . the wh/lsb ratio for this meter is 6.378 10 ?4 using equation 35 with wdiv at the default value. (imp/wh) ) 1 ( ) 1 ( lsb wh ant meterconst wdiv cfden cfnum + + = 4 10 378 . 6 2 . 3 490 1 imp/wh 200 . 3 ) 1 490 ( 1 lsb wh ? = = + = calibrating watt gain using an accurate source example the cfden value calculated using equation 40 should be written to the cfden register before beginning calibration and zero should be written to the cfnum register. enable the line accumulat ion mode and the line accumulation interrupt. then, write the number of half line cycles for the energy accumulation to the linecyc register to set the accumulation time. reset the interrupt status register and wait for the line cycle accumulation interrup t. the first line cycle accumulation results might not use the accumulation time set by the linecyc register and , therefore, should be discarded. after resetting the interrupt status register, the following line cycle readings will be valid. when linecyc h alf line cycles have elapsed, the irq pin goes active low and the nominal laenergy with the test current applied can be read. this laenergy value is compared to the expected laenergy value to determine the wgain value. if apparent en ergy gain calibration is performed at the same time, lvaenergy can be read directly after laenergy. both registers should be read before the next interrupt is issued on the irq pin. figure 72 details steps to calibrate the watt gain using an accurate source.
ade7763 data sheet rev . c | page 38 of 56 write wgain value to the wgain register: addr. 0x12 calculate cfden value for design write cfden value to cfden register addr. 0x15 = cfden set half line cycles for accumulation in linecyc register addr. 0x1c set i test = i b , v test = v nom , pf = 1 calculate wgain. see equation 43. set mode for line cycle accumulation addr. 0x09 = 0x0080 enable line cycle accumulation interrupt addr. 0x0a = 0x04 read line accumulation energy addr. 0x04 reset the interrupt status read register addr. 0x0c interrupt? no no yes yes 04481-a-086 reset the interrupt status read register addr. 0x0c interrupt? figure 72 . calibrating watt gain using an accurate source equation 43 describes the relationship between the expected laenergy value and the laenergy measured in the test conditi on: wgain = int ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 12 ) ( ) ( 2 1 nominal ib expected ib laenergy laenergy (4 3 ) the nominal laenergy reading, laenergy ib ( nominal ) , is the laenergy reading with the test current applied. the expected laenergy reading is calculated from the following equation: laenergy ib ( expected ) = int ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + wdiv cfden cfnum time on accumulati cf expected ib 1 1 (s) ) ( (4 4 ) where cf ib ( expected ) ( hz) is calculated from equation 30, accumulation time is calculated from equation 33, and the line period is determined from the period register according to equation 34 . for this example: meter constan t: mete rconstant ( imp/wh) = 3.2 test current: i b = 10 a line voltage: v nominal = 220 v line frequency: f l = 50 hz half line cycles: linecyc ib = 2000 cf numerator: cfnum = 0 cf denominator: cfden = 489 energy reading at base current: laenergy ib ( nominal ) = 17174 period register reading: period = 8959 clock frequency: clkin = 3.579545 mhz cf expected is calculated to be 1.9556 hz according to equation 30. laenergy expected is calculated to be 19186 using equat ion 44. cf ib ( expected ) (hz) = ) cos( s/h 3600 a 10 v 220 imp/wh 200 . 3 ? = 1.9556 hz laenergy ib ( expected ) = int ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + wdiv cfden cfnum clkin period linecyc cf ib expected ib 1 1 / 8 2 / ) ( laenergy ib ( expected ) = int 1 1 489 1 ) 10 579545 . 3 /( 8 8959 2 / 2000 9556 . 1 6 ? ? ? ? ? ? ? ? ? ? ? ? + = 19186 ) 4 . 19186 ( = int wgain is calculated to be 480 using equation 43.
data sheet ade7763 rev. c | page 39 of 56 wgain = i nt 480 2 1 17174 19186 12 = ? ? ? ? ? ? ? ? ? ? ? ? ? note that wgain is a signed, twos complement register. with wdiv and cfnum set to 0, laenergy can be expressed as laenergy ib ( expected ) = )) 1 ( / 8 2 / ( ) ( + cfden clkin period linecyc cf int ib expected ib the calculated wh/lsb ratio for the active energy register, using e quation 35 is 6. 378 10 ? 4 is 4 10 378 . 6 imp/wh 200 . 3 ) 1 489 ( 1 lsb wh ? = + = watt offset offset calibration allows outstanding performance over a wide dynamic range, for example, 1000:1. to do this calibration two measurements are needed at unity power factor, one at i b and the other at the lowest current to be corrected. either calibra - tion frequency or line cycle accumulation measurements can be used to determine the energy offset. gain calibration should be performed prior to offset calibration. offset calibration is performed by determining the active energy error rate. after determining the active energy error rate, calcu - late the value to write to the apos register to correct the offset. apos = ? clkin rate error aenergy 35 2 (4 5 ) the aenergy registers update at a rate of clkin/4 . the twos complement apos register provides a fine adjustment to the active power calculation. it represents a fixed amount of power offset to be adjusted every clkin/4 . the 8 lsbs of the apos register are fractional such that one lsb of apos represents 1/256 of the least significant bit of the internal active energy register. therefore, one lsb of the apos register represents 2 ? 33 of the aenergy[23:0] active energy register. s ee the following sections for steps to determine the active energy error rate for both line accumulation and reference meter calibration options. calibrating watt offset using a reference meter example figure 73 shows the steps inv olved in calibrating watt offset with a reference meter. write apos value to the apos register: addr. 0x11 measure the % error between the cf output and the reference meter output, and the load in watts set i test = i min , v test = v nom , pf = 1 04481-a-087 calculate apos. see equation 45. figure 73 . calibrating watt offset u sing a reference meter for this example: meter constant: meterconstant (imp/wh) = 3.2 minimum current: i min = 40 ma load at minimum cur rent : w imin = 9.6 w cf error at minimum current: % error cf ( imin ) = 1.3 % cf numerator: cfnum = 0 cf denominator: c den = 489 clock frequency: c kin = 3.579545 mhz using equation 45 , apos is ? 522 for this example. cf absolute error = cf imin ( nominal ) ? cf imin ( e xpected ) (46 ) cf absolute error = (% error cf ( imin ) ) w imin 3600 (imp/wh) ant meterconst (47) cf absolute error = hz 000110933 . 0 3600 200 . 3 6 . 9 100 % 3 . 1 = ? ? ? ? ? ? then, aenergy error rate (lsb/s) = cf absolute error 1 1 + + cfnum cfden (48) aenergy error rate (lsb/s) = 0.000110933 05436 . 0 1 490 = using equation 45, apos is ? 522. apos = ? 522 10 579545 . 3 2 05436 . 0 6 35 ? = apos can be repre s ented as follows with cfnum and wdiv set at 0: apos = ? clkin cfden ant meterconst w error imin imin cf 35 ) ( 2 ) 1 ( 3600 (imp/wh) ) (% +
ade7763 data sheet rev . c | page 40 of 56 calibrating watt offset with an accurate source example figure 74 is the flowchart for w att o ffset calibration with an accurate source. set half line cycles for accumulation in linecyc register addr. 0x1c set i test = i min , v test = v nom , pf = 1 calculate apos. see equation 45. set mode for line cycle accumulation addr. 0x09 = 0x0080 enable line cycle accumulation interrupt addr. 0x0a = 0x04 read line accumulation energy addr. 0x04 reset the interrupt status read register addr. 0x0c interrupt? no no yes yes reset the interrupt status read register addr. 0x0c interrupt? write apos value to the apos register: addr. 0x11 04481-a-088 figure 74 . calibrating watt offset with an accurate source for this example : meter constant: meterconstant (i mp/ wh) = 3.2 line voltage: v nominal = 220 v line frequency: f l = 50 hz cf numerator: cfnum = 0 cf denominator: cfden = 4 89 base current: i b = 10 a half line cycles used at base current: linecyc ( ib ) = 2000 period register reading: period = 8959 clock frequency: clkin = 3.579545 mhz expected laenergy register value a t bas e current (from the watt gain section): laenergy ib ( expected ) = 19186 minimum current: i min = 40 ma number of half line cycles used at minimum current: linecyc ( imin ) = 35700 active e nergy reading a t minimum current: laenergy imin ( nominal ) = 1395 the laenergy expected at i min is 1255 using equation 49. laenergy imin ( expected ) = int ? ? ? ? ? ? ? ? ib min expected ib b min linecyc linecyci laenergy i i ) ( ( 49) laenergy imin ( expected ) = int 1370 ) 80 . 1369 ( 2000 35700 19186 10 04 . 0 = = ? ? ? ? ? ? int where: laenergy ib ( expected ) is the expected laenergy reading at i b from the watt gain calibration. linecyc imin is the number of half line cycles that energy is accumulated over when measuring at i min . more line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. for examp le, if a test current of 40 ma results in an active energy accumulation of 113 after 2000 half line cycles, one lsb variation in this reading represents a 0.8% error. this measurement does not provide enough resolution to calibrate a <1% offset error. howe ver, if the active energy is accumulated over 37,500 half line cycles, one lsb variation results in 0.05% error, reducing the quantization error. apos is ? 672 using equations 55 and 49 . laenergy absolute error = laenergy imin ( nominal ) ? laenergy imin ( expec ted ) laenergy absolute error = 1395 ? 1370 = 25 ( 50) aenergy error rate (lsb/s) = period clkin linecyc error absolute laenergy 8 2 / (5 1 ) aenergy error rate (lsb/s) = 069948771 . 0 8959 8 10 579545 . 3 2 / 35700 25 6 = apos = ? clkin rate error aenergy 35 2 apos = ? 672 10 579545 . 3 2 069948771 . 0 6 35 ? =
data sheet ade7763 rev. c | page 41 of 56 phase calibration the phca l register is provided to remove small phase errors. the ade7763 compensates for phase error by inserting a small time delay or advance on the voltage channel input. phase leads up to 1.84 and phase lags up to 0.72 at 50 hz can be corrected. the error is determined by measuring the active energy at i b and two power factors, pf = 1 and pf = 0.5 inductive. some cts may introduce large phase errors that are beyond the range of the phase calibration register. in this case, coarse phase compensation has to be done externally with an analog filter. the phase error can be obtained from either cf or laenergy measurements: error = 2 2 ) ( ) ( 5 . 0 , expected ib expected ib pf ib laenergy laenergy laenergy ? = (5 2 ) if w att gain and offset calibration have been performed, there should be 0% error in cf at unity power fa ctor , and then error = % error cf ( ib,pf = 0.5) /100 (5 3 ) the phase error is phase error () = ?arcsin ? ? ? ? ? ? ? ? 3 error (5 4 ) the relationship between phase error and the phcal phase correction register is phcal = int ( ) + ? ? ? ? ? ? 360 period error phase 0x0d (5 5 ) the expression for phcal can be simplified using the assumption that at small x arcsin( x ) x the delay introduced in the voltage channel by phcal is delay = ( phcal ? 0x0d) 8/ clkin (56 ) the delay associated with the phc al register is a time delay if phcal ? 0x0d is positive , but represents a time advance if this quantity is negative. ther e is no time delay if phcal = 0x0d. the phase correction is in the opposite direction of the phase error. phase correction () = ? ( phcal ? 0x0d) period 360 ( 57) calibrating phase using a reference meter example a power factor of 0.5 induct ive can be assumed if the pulse output rate of the reference meter is half of its pf = 1 rate. then , the percent error between cf and the pulse output of the reference meter can be used to perform the preceding calculations. write phcal value to the phcal register: addr. 0x10 measure the % error between the cf output and the reference meter output set i test = i b , v test = v nom , pf = 0.5 04481-a-089 calculate phcal. see equation 55. figure 75 . calibrating phase using a reference meter for this example: cf %error at pf = 0.5 inductive: % error cf ( ib,pf = 0.5 ) = 0.215% period register reading: period = 8959 then phcal is 11 using equation s 57 through 59: error = 0.215%/100 = 0.00215 phase error () = ?arcsin ? = ? ? ? ? ? ? ? ? 07 . 0 3 00215 . 0 phcal = int ? ? ? ? ? ? ? 360 8959 07 . 0 + 0x0d = ?2 + 13 = 11 phcal can be expressed as follows: phcal = int ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 3 100 % a r csin period error + 0x0d ( 58) note that phcal is a signed , twos complement register. setting the phcal register to 11 provides a phase correction of 0.08 to correct the phase lead: phase correction () = ? period phcal ? 360 ) 0x0d ( phase correction () = ? = ? 08 . 0 8960 360 ) 0x0d 11 (
ade7763 data sheet rev . c | page 42 of 56 calibrating phase with an accurate source example with an accurate source, line cycle accumulation is a good method of calibrating phase error. the value of laenergy must be obtained at two power factors, pf = 1 and pf = 0.5 inductive. set half line cycles for accumulation in linecyc register addr. 0x1c set i test = i b , v test = v nom , pf = 0.5 calculate phcal. see equation 55. set mode for line cycle accumulation addr. 0x09 = 0x0080 enable line cycle accumulation interrupt addr. 0x0a = 0x04 read line accumulation energy addr. 0x04 reset the interrupt status read register addr. 0x0c interrupt? no no yes yes reset the interrupt status read register addr. 0x0c interrupt? write phcal value to the phcal register: addr. 0x10 04481-a-090 figure 76 . calibrating phase with an accurate source for this example: meter constant: meterconstant (imp/wh) = 3.2 line voltage: v nominal = 220 v line frequency: f l = 50 hz cf numerator: cfnum = 0 cf denominator: cfden = 489 base current: i b = 10 a half line cycles used at base current: linecyc ib = 2000 period reg ister: period = 8959 expected line accumulation at unity power factor (from watt gain section): laenergy ib ( expected ) = 19186 active energy reading at pf = 0 .5 inductive: laenergy ib, pf = 0 .5 = 9613 the error using equation 52 is error = 0021 . 0 2 19186 2 19186 9613 = ? phase error () = ?arcsin ? = ? ? ? ? ? ? ? ? 07 . 0 3 0021 . 0 using equation 55 , phcal is 11. phcal = int 11 13 2 0x0d 360 8959 07 . 0 = + ? = + ? ? ? ? ? ? ? note that phcal is a signed , twos complement register. the phase lead is corrected by 0.08 degrees when the phcal register is set to 11: phase correc tion () = ? period phcal ? 360 ) 0x0d ( phase correction () = ? = ? 08 . 0 8960 360 ) 0x0d 11 ( vrms and irms calibration v rms and i rms are calculated by squaring the input in a digital multiplier. ) 2 cos( ) sin( v 2 ) sin( v 2 ) ( t v v t t t v 2 2 2 ? = = (59) the square of the rms value is extracted from v 2 ( t ) by a low - pass filter. the square root of the output of this low - pass filter gives the rms value. an offset correction is provided to cancel noise and offset contributions from the input . there is ripple noise from the 2 term because the low - pa ss filter does not completely attenuate the signal. this noise can be minimized by synchronizing the rms register readings with the zero crossing of the voltage signal. the irq output can be configured to indicate the zero crossing o f the voltage signal. this flowchart demonstrates how v rms and i rms readings are synchronized to the zero crossings of the voltage input. set interrupt enable for zero crossing addr. 0x0a = 0x0010 reset the interrupt status read register addr. 0x0c interrupt? no yes 04481-a-091 read vrms or irms addr. 0x17; 0x16 reset the interrupt status read register addr. 0x0c figure 77 . synchronizing v rms and i rms readings with zero crossings
data sheet ade7763 rev. c | page 43 of 56 voltage rms compensat ion is done after the square root. v rms = vrms0 + vrmsos (60 ) where: vrms0 is the rms measurement without offset correction . vrms is linear from full - scale to full - scale/20. to calibrate the offset, two vrms measurements are required, for example, at v no minal and v nominal /10. v nominal is set at half of the full - scale analog input range so that the smallest linear vrms reading is at v nominal /10. vrmsos = 1 2 2 2 1 v v vrms v vrms v ? ? 1 (61) where v rms 1 and v rms 2 are rms register values without offset correction fo r input v 1 and v 2 , respectively . if the range of the 12 - bit, twos complement vrmsos register is not enough, use the voltage channel offset register, ch2os , to correct the vrms offset. current rms compensation is p erformed before the square root: irms 2 = i rms0 2 + 32768 irmsos (62) where irms0 is the rms measure ment without offset correction. the current rms calculation is linear from full scale to full scale/100. to calibrate this offset, two irms measurements are required, for example, at i b and i max /50 . i max is set at half of the full - scale analog input range so that the smalles t linear i rms reading is at i max /50. irmsos = 2 1 2 2 2 1 2 2 2 2 2 1 i i irms i irms i ? ? 32768 1 (63) where irms 1 and irms 2 are rms register values without offset correction for input i 1 and i 2 , respective ly . apparent energy apparent energy gain calibration is provided for both meter - to - meter gain adjustment and for setting the vah/lsb constant. vaenergy = ? ? ? ? ? ? + 12 2 1 1 vagain vadiv vaenergy initial (64) vadiv is similar to the cfden for the watt - hour calibration. it should b e the same across all meters and determines the vah/lsb constant. vaga in is used to calibrate individual meters. apparent energy gain calibration should be performed before rms offset correction to make the most efficient use of the current test points. ap parent energy gain and watt gain compensation require testing at i b , while rms and watt offset correction require a lower test current. apparent energy gain calibration can be done simultaneously with the w att - hour gain calibration using line cycle accumu lation . in this case, laenergy and lva e n e rg y , the line cycle accumulation apparent energy register s , are both read following the line cycle accumulation interrupt. figure 78 shows a flowchart for calibrating active and apparent ene rgy simultaneously. vagain = int ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 12 ) ( ) ( 2 1 nominal ib expected ib lvaenergy lvaenergy (6 5 ) lva e n e rg y ib ( expected ) = int ? ? ? ? ? ? ? ? ? ? ? ? ) ( s/h 3600 s time on accumulati constant lsb vah i v b nominal ( 66) the accumulation time is determined from equation 33, and the line period can be determined from the period register accord ing to equation 34 . the vah represented by the vaenergy register is vah = vaenergy vah / lsb constant ( 67) the vah /l sb constant can be verified using this equation: lvaenergy s time on accumulati va constant lsb vah 3600 ) ( = (68)
ade7763 data sheet rev . c | page 44 of 56 calculate cfden value for design write cfden value to cfden register addr. 0x15 = cfden set half line cycles for accumulation in linecyc register addr. 0x1c set i test = i b , v test = v nom , pf = 1 calculate wgain. see equation 43. set mode for line cycle accumulation addr. 0x09 = 0x0080 enable line cycle accumulation interrupt addr. 0x0a = 0x04 read line accumulation energy active energy: addr. 0x04 apparent energy: addr. 0x07 reset the interrupt status read register addr. = 0x0c interrupt? no no yes yes 04481-a-092 reset the interrupt status read register addr. = 0x0c interrupt? write wgain value to addr. 0x12 calculate vagain. see equation 65. write vgain value to addr. 0x1a figure 78 . active/apparent gain calibration cl kin frequency in this data sheet, the characteristics of the ade7763 are shown when clkin frequency equals 3.579545 mhz. however, the ade7763 is designed to have the same accuracy at any clkin frequency within the specified range. if the clkin frequency is not 3.579545 mhz, various timing and filter characteristics will need to be redefined with the new clkin frequency. for example, the cutoff frequencies of all digital filters, such as lpf1, lpf2, or hpf1, shift in proportion to the change in clkin frequen cy according to the following equation: mhz 579545 . 3 frequency clkin frequency original frequency new = (69) the change in clkin frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with the serial clock sig nal (sclk). however, it is important to observe the read/write timing of the serial data transfer see the timing characteristics in table 2 . table 8 lists various timing changes that are affected by clkin f requency. table 8 . frequency dependencies of the ade7763 parameters parameter clkin dependency nyquist frequency for ch 1 , ch 2 adcs clkin/8 phcal resolution (seconds per lsb) 4/clkin active energy register update rate (hz) clkin /4 waveform sampling rate (per second) wavsel 1,0 = 0 0 clkin/128 0 1 clkin/256 1 0 clkin/512 1 1 clkin/1024 maximum zxtout period 524,288/clkin
data sheet ade7763 rev. c | page 45 of 56 suspending functionality the analog and the digital circuit can be suspended separately. the analog portion can be suspended by setting the asuspend bit (bit 4) of the mode register to logic highsee the mode register (0x09) section. in suspend mode, all waveform samples from the adcs are set to 0s. the digital circuitry can be halted by stopping the clkin input and maintaining a logic high or low on the clkin pin. the ade7763 can be reactivated by restoring the clkin input and setting the asuspend bit to logic low. checksum register the ade7763 has a checksum register (checksum[5:0]) to ensure that the data bits received in the last serial read operation are not corrupted. the 6-bit checksum register is reset before the first bit (msb of the register to be read) is put on the dout pin. during a serial read operat ion, when each data bit becomes available upon the rising edge of sclk, the bit is added to the checksum register. at the end of the serial read operation, the content of the checksum register is equal to the sum of all ones previously read in the register. using the checksum register, the user can determine if an error has occurred during the last read operation. note that a read to the checksum register also generates a checksum of the checksum register itself. content of register (n-bytes) checksum register addr: 0x3e + + dout 04481-a-070 figure 79. checksum register for serial interface read serial interface all ade7763 functionality is accessible via several on-chip registerssee figure 80. the contents of these registers can be updated or read using the on-chip serial interface. after power- on or toggling the reset pin low and a falling edge on cs , the ade7763 is placed in communication mode. in communica- tion mode, the ade7763 expects a write to its communication register. the data written to the communication register determines whether the next data transfer operation is a read or a write and which register is accessed. therefore, all data transfer operations with the ade7763, whether a read or a write, must begin with a write to the communication register. communication register in out in out in out in out in out register 1 register 2 register 3 register n?1 register n register address decode din dout 04481-a-071 figure 80. addressing ade7763 registers via the communication register the communication register is an 8-bit-wide register. the msb determines whether the next data transfer operation is a read or a write. the 6 lsbs contain the address of the register to be accessedsee the communication register section for a more detailed description. figure 81 and figure 82 show the data transfer sequences for a read and write operation, respectively. a data transfer is complete when the lsb of the ade7763 register being addressed (for a write or a read) is transferred to or from the ade7763. when multiple reads or writes occur in succession, a time delay of 2600 ns must be included between the last falling sclk edge on the first read or write to the first sclk falling edge of the next read or write. , during that delay time, the cs pin must be high for at least 100 ns. multibyte communication register write din sclk cs dou t read data address 00 04481-a-072 figure 81. reading data from the ade7763 via the serial interface communication register write din sclk cs address 01 04481-a-073 multibyte read data figure 82. writing data to the ade7763 via the serial interface
ade7763 data sheet rev. c | page 46 of 56 the serial interface of the ade7763 is made up of four signals: sclk, din, dout, and cs . the serial clock for a data transfer is applied at the sclk logic input. this logic input has a schmitt- trigger input structure that allows slow rising and falling clock edges to be used. all data transfer operations are synchronized to the serial clock. data is shifted into the ade7763 at the din logic input upon the falling edge of sclk. data is shifted out of the ade7763 at the dout logic output upon a rising edge of sclk. the cs logic input is the chip-select input. this input is used when multiple devices share the serial bus. a falling edge upon cs also resets the serial interface and places the ade7763 into communication mode. the cs input should be driven low for the entire data transfer operation. bringing cs high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. the cs logic input can be tied low if the ade7763 is the only device on the serial bus. however, with cs tied low, all initiated data transfer operations must be fully completed, i.e., the lsb of each register must be transferred because there is no other way to bring the ade7763 into commu- nication mode without resetting the entire device using reset . ade7763 serial write operation the serial write sequence takes place as follows. with the ade7763 in communication mode (i.e., the cs input logic low), first a write to the communication register occurs. the msb of this byte transfer is a 1, indicating that the data transfer operation is a write. the lsbs of this byte contain the address of the register to be written to. the ade7763 starts shifting in the register data upon the next falling edge of sclk. all remaining bits of register data are shifted in upon the falling edge of subsequent sclk pulsessee figure 83. as explained earlier, the data write is initiated by a write to the communication register followed by the data. during a data write operation, data is transferred to all on-chip registers one byte at a time. after a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ade7763 on-chip registers. although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer should not finish until at least 4 s after the end of the previous byte transfer. this functionality is expressed in the timing specification t 6 see figure 83. if a write operation is aborted during a byte transfer ( cs is brought high), then that byte cannot be written to the destination register. destination registers can be up to 3 bytes widesee table 9, table 10, table 11, table 12, and table 13. therefore the first byte shifted into the serial port at din is transferred to the msb (most significant byte) of the destination register. if, for example, the addressed register is 12 bits wide, a 2-byte data transfer must take place. because the data is always assumed to be right justified, in this case the 4 msbs of the first byte would be ignored and the 4 lsbs of the first byte written to the ade7763 would be the 4 msbs of the 12-bit word. figure 84 illustrates this example. din sclk cs t 2 t 3 t 1 t 4 t 5 t 7 t 6 t 8 command byte most significant byte least significant byte 10 a4a5 a3 a2 a1 a0 db7 db0 db7 db0 t 7 04481-a-074 figure 83. serial interface write timing sclk din x x x x db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 most significant byte least significant byte 04481-a-075 figure 84. 12-bit serial write operation
data sheet ade7763 rev. c | page 47 of 56 serial read operation during a data read operation from the ade7763, data is shifted out at the dout logic output upon the rising edge of sclk. as is the case with the data write operation, a write to the commu- nication register must precede a data read. with the ade7763 in communication mode ( cs logic low), first an 8-bit write to the communication register occurs. the msb of this byte transfer is a 0, indicating that the next data transfer operation is a read. the lsbs of this byte contain the address of the register that is to be read. the ade7763 starts shifting data out of the register upon the next rising edge of sclksee figure 85. at this point, the dout logic output leaves its high impedance state and starts driving the data bus. all remaining bits of register data are shifted out upon subsequent sclk rising edges. the serial interface also enters communica- tion mode as soon as the read is complete. then, the dout logic output enters a high impedance state upon the falling edge of the last sclk pulse. the read operation can be aborted by bringing the cs logic input high before the data transfer is complete. the dout output enters a high impedance state upon the rising edge of cs . when an ade7763 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. this allows the ade7763 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. note that when a read operation follows a write operation, the read command (i.e., write to communication register) should not happen for at least 4 s after the end of the write operation. if the read command is sent within 4 s of the write operation, the last byte of the write operation could be lost. this timing constraint is given as timing specification t 9 . sclk cs t 1 t 10 t 13 0 0 a4a5 a3 a2 a1 a0 db0 db7 db0 db7 din dout t 11 t 11 t 12 command byte most significant byte least significant byte t 9 04481-a-076 figure 85. serial interface read timing
ade7763 data sheet rev . c | page 48 of 56 registers table 9 . summary of registers by address address name r/w no. bits default type 1 description 0x01 waveform r 24 0x0 s waveform register. when wsmp (bit 3) in the i nterrupt e nable register i s set to 1 , t his read - only register contains the sampled waveform data from either channel 1, channel 2, or the active power signal. the data source and the length of the waveform registers are selected by bits 14 and 13 in the mode register see the channel 1 sampling and channel 2 sampling sections. 0x02 aenergy r 24 0x0 s active energy register. active power is accumulated (integrated) over time in this 24 - bit, read - only register see the energy calculation section. 0x03 raenergy r 24 0x0 s same as the active energy register , except that the register is reset to 0 following a read operation. 0x04 laenergy r 24 0x0 s line accumulation active energy register. the instantaneous activ e power is accumulated in this read - only register over the lin e cyc number of half line cycles. 0x05 vaenergy r 24 0x0 u apparent energy register. apparent power is accumulated over time in this read - only register. 0x06 rvaenergy r 24 0x0 u same as the va energy register , except that the register is reset to 0 following a read operation. 0x07 lvaenergy r 24 0x0 u line accumulation apparent energy register. the instantaneous real power is accumulated in this read - only register over the linecyc number of hal f line cycles. 0x08 reserved 0x09 mode r/w 16 0x000c u mode register. this is a 16 - bit register through which most of the ade7763s functionality is accessed. signal sample rates, filter enabling, and calibration modes are selected by writing to thi s register. the contents can be read at any time see the mode register (0 x 09) section. 0x0a irqen r/w 16 0x40 u interrupt enable register. ade7763 interrupts can be deactivated at any time by setting th e corresponding bit in this 16- bit enable register to logic 0. the status register continues to detect an interrupt event even if disabled ; h owever, the irq output is not activated see the interrupts section. 0x0b status r 16 0x0 u inter ru pt status register. this is a 16- bit read - only register that contains information regarding the source of ade7763 interrupts see the interrupts section. 0x0c rststatus r 16 0x0 u same as the interrupt status register , except that the register contents are reset to 0 (all flags cleared) after a read operation. 0x0d ch1os r/w 8 0x00 s * channel 1 offset adjust. bit 6 is not used. writing to bits 0 to 5 allows offsets on channel 1 to be removed see the analog i nputs and ch1os register sections. writing logic 1 to the msb of this register enables the digital integrator on channel 1 ; writing logic 0 disables the integrator. the default value of this bit is 0. 0x0e ch2os r/w 8 0x0 s * channel 2 offset adjust. bits 6 and 7 are not used. writing to bits 0 to 5 of this register allows offsets on channel 2 to be removed see the analog inputs section. note that the ch2os register is invert ed. to apply a positive offset, a negative number is written to this register. 0x0f gain r/w 8 0x0 u pga gain adjust. this 8 - bit register is used to adjust the gain selection for the pga in channels 1 and 2 see the analog inputs section. 0x10 phcal r/w 6 0x0d s phase calibration register. the phase relationship between channel 1 and 2 can be adjusted by writing to this 6 - bit register. the valid content of this t wos comple ment register is be tween 0x1d to 0x21. at the line frequency of 60 hz, this range s from C 2.06 to +0.7 see the phase compensation section.
data sheet ade7763 rev. c | page 49 of 56 address name r/w no. bits default type 1 description 0x11 apos r/w 16 0x0 s active power offset correction. this 16 - bit register allows small offs ets in the active power calculation to be removed see the active power calculation section. 0x12 wgain r/w 12 0x0 s power gain adjust. this is a 12 - bit register. calibrate t he active power calculation by writing to this register. the calibration range is 50% of the nominal full - scale active power. the resolution of the gain adjust is 0.0244%/lsb see the calibrating an energy meter section. 0x13 wdiv r/w 8 0x0 u active energy divider regis ter. the internal active energy register is divided by the value of this register before being stored in the aenergy register. 0x14 cfnum r/w 12 0x3f u cf frequency divider numerator register. a djust t he output frequency on the cf pin by writing to this 1 2 - bit read/write register see the energy - to - frequency conversion section. 0x15 cfden r/w 12 0x3f u cf frequency divider denominator register. a djust t he output frequency on the cf pin by writing to this 12 - bit read/write register see the energy - to - frequency conversion section. 0x16 irms r 24 0x0 u channel 1 rms value (current channel). 0x17 vrms r 24 0x0 u channel 2 rms value (voltage channel). 0x18 irmsos r/w 12 0x0 s channel 1 rms offset correction r egister. note that for correct operation only positive values should be written to the irmsos register. 0x19 vrmsos r/w 12 0x0 s channel 2 rms offset correction register. 0x1a vagain r/w 12 0x0 s apparent gain register. c alibrat e the a pparent power calcu lation by writing to this register. the calibration range is 50% of the nominal full - scale real power. the resolution of the gain adjust is 0.02444%/lsb. 0x1b vadiv r/w 8 0x0 u apparent energy divider register. the internal apparent energy register is div ided by the value of this register before being stored in the vaenergy register. 0x1c linecyc r/w 16 0xffff u line cycle energy accumulation mode line - cycle register. this 16 - bit register is used during line cycle energy accumulation mode to set the numbe r of half line cycles for energy accumulation see the line cycle energy accumulation mode section. 0x1d zxtout r/w 12 0xfff u zero - cross ing timeout. if no zero crossings are detected on channel 2 within the time specified in this 12- bit register, the interrupt request line ( irq ) will be activated see the zero - crossing detection section. 0x1e sagcyc r/w 8 0xff u sag line cycle register. this 8 - bit register specifies the nu mber of consecutive line cycles below saglvl that is required on channel 2 before the sag output is activated see the line voltage sag detection section. 0x1f saglvl r/w 8 0x0 u sag voltage level. an 8 - bit write t o this register determines at what peak signal level on channel 2 the sag pin becomes active. the signal must remain low for the number of cycles specified in the sagcyc register before the sag pin is activated see the line voltage sag detection section. 0x20 ipklvl r/w 8 0xff u channel 1 peak level threshold (current channel). this register sets the level of current peak detection. if the channel 1 input exceeds this level, the p ki flag in the status register is set. 0x 2 1 vpklvl r/w 8 0xff u channel 2 peak level threshold (voltage channel). this register sets the level of voltage peak detection. if the channel 2 input exceeds this level, the pkv flag in the status register is se t. 0x22 ipeak r 24 0x0 u channel 1 peak register. the maximum input value of the current channel , since the last read of the register is stored in this register. 0x23 rstipeak r 24 0x0 u same as channel 1 p eak r egister , except that the register contents are reset to 0 after a read. 0x24 vpeak r 24 0x0 u channel 2 peak register. the maximum input value of the voltage channel , since the last read of the register is stored in this register. 0x25 rstvpeak r 24 0x0 u same as channel 2 p eak r egister , except t hat the register contents are reset to 0 after a read.
ade7763 data sheet rev . c | page 50 of 56 address name r/w no. bits default type 1 description 0x26 temp r 8 0x0 s temperature register. this is an 8 - bit register that contains the result of the latest temperature conversion see the temperature measurement section. 0x 27 period r 16 0x0 u period of the channel 2 (voltage channel) input estimated by zero - crossing processing. the msb of this register is always zero. 0x28 C 0x3c reserved. 0x3d tmode r/w 8 C u test mode register. 0x3e chksum r 6 0x0 u checksum registe r. this 6 - bit , read - only register is equal to the sum of all the ones in the previous read s see the serial read operation section. 0x3f dierev r 8 C u die revision register. this 8 - bit , read - only register contains the revision num ber of the silicon. 1 type decoder: u = unsigned, s = signed by twos complement method, and s * = signed by sign magnitude method.
data sheet ade7763 rev. c | page 51 of 5 6 register description s all ade7763 functionality is accessed via on - chip registers. each register is accessed by first writing to the communication register and then transferring the register data. a full description of the serial i nterface protocol is given in the serial interface section. communication regist er the communication register is an 8 - bit, write - only register that controls the serial data transfer between the ade7763 and the host processor. all d ata transfer operations must begin with a write to the communication register. the data written to the communication register determines whether the next operation is a read or a write and which register is being accessed. table 10 outlines the bit designations for the communication register. db7 db6 db5 db4 db3 db2 db1 db0 w/r 0 a5 a4 a3 a2 a1 a0 table 10 . communication register bit location bit mnemonic description 0 to 5 a0 to a5 the 6 lsbs of the commu nication register specify the register for the data transfer operation. table 9 lists the address of each on - chip register. 6 reserved this bit is unused and should be set to 0. 7 w/r when this bit is a logic 1, the data transf er operation immediately following the write to the communication register is interpreted as a write to the ade7763. when this bit is a logic 0, the data transfer operation immediately following the write to the communication register is interpreted as a r ead operation. mode register (0 x 09) the ade7763 functionality is configured by writing to the mode register. table 11 describes the functionality of each bit in the register. table 11. bit location bit mnemonic default value description 0 dishpf 0 hpf (high - pass filter) in channel 1 is disabled when this bit is set. 1 dislpf2 0 lpf (low - pass filter) after the multiplier (lpf2) is disabled when this bit is set. 2 discf 1 frequency output cf is disabl ed when this bit is set. 3 dissag 1 line voltage sag detection is disabled when this bit is set. 4 asuspend 0 by setting this bit to logic 1, both a/d converters can be turned off. during normal operation, this bit should be left at logic 0. all digital functionality can be stopped by suspending the clock signal at clkin pin. 5 tempsel 0 temperature conversion starts when this bit is set to 1. this bit is automatically reset to 0 after the temperature conversion. 6 swrst 0 software chip reset. a data tr ansfer should not take place to the ade7763 for at least 18 s after a software reset. 7 cycmode 0 setting this bit to logic 1 places the chip in line cycle energy accumulation mode. 8 disch1 0 adc 1 (channel 1) inputs are internally shorted together. 9 disch2 0 adc 2 (channel 2) inputs are internally shorted together. 10 swap 0 by setting this bit to logic 1, the analog inputs v2p and v2n are connected to adc 1 and the analog inputs v1p and v1n are connected to adc 2. 12, 11 dtrt1, 0 00 use these bits to select the waveform register update rate. dtrt1 dtrt0 update rate 0 0 27.9 ksps (clkin/128) 0 1 14 ksps (clkin/256) 1 0 7 ksps (clkin/512) 1 1 3.5 ksps (clkin/1024)
ade7763 data sheet rev . c | page 52 of 56 bit location bit mnemonic default value description 14, 13 wavsel1, 0 00 use these bits to select the source of the s ampled data for the waveform register. wavsel1, 0 length source 0 0 24 bits, active power signal (output of lpf2) 0 1 reserved 1 0 24 bits, channel 1 1 1 24 bits, channel 2 15 poam 0 writing logic 1 to this bit allows only posi tive active power to accumulate. the default value of this bit is 0. swap (swap ch1 and ch2 adcs) dtrt (waveform samples output data rate) 00 = 27.9ksps (clkin/128) 01 = 14.4ksps (clkin/256) 10 = 7.2ksps (clkin/512) 11 = 3.6ksps (clkin/1024) poam (positive only accumulation) wavsel (waveform selection for sample mode) 00 = lpf2 01 = reserved 10 = ch1 11 = ch2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr: 0x09 dishpf (disable hpf1 in channel 1) dislpf2 (disable lpf2 after multiplier) discf (disable frequency output cf) dissag (disable sag output) asuspend (suspend ch1 and ch2 adcs) tempsel (start temperature sensing) swrst (software chip reset) cycmode (line cycle energy accumulation mode) disch2 (short the analog inputs on channel 2) disch1 (short the analog inputs on channel 1) note: register contents show power-on defaults 04481-a-077 figure 86 . mode register
data sheet ade7763 rev. c | page 53 of 56 interrupt status reg ister (0 x 0b), reset interrupt stat us register (0 x 0c), interrupt enable reg ister (0 x 0a) the status register is used by the mcu to determine the source of an interrupt request ( irq ). when an interrupt event occurs, the corresponding flag in the interrupt status register is set to logic high. if the enable bit for this flag is logic 1 in the interr upt enable register, the irq logic output will go active low. when the mcu services the interrupt, it must first carry out a read from the interrupt statu s register to determine the source of the interrupt. table 12. bit location interrupt flag description 0 aehf indicates that an interrupt occurred because the active energy register, aenergy , is more than half full. 1 sag indicates that an interrupt was caused by a sag on the line voltage. 2 cycend indicates the end of energy accumulation over an integral number of half line cycles, as defined by the content of the linecyc register see the line cycle energy accumulation mode section. 3 wsmp indicates that new data is present in the w aveform register. 4 zx this status bit is set to 1 on the rising and falling edge of the voltage waveform, see the zero - crossing detection section. 5 temp indicates that a temperature conversion result is available in the tempera ture register. 6 reset indicates the end of a reset for software and hardware resets. the corresponding enable bit has no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but cannot be enabled to cause an inte rrupt. 7 aeof indicates that the active energy register has overflowed. 8 pkv indicates that the waveform sample from channel 2 has exceeded the vpklvl value. 9 pki indicates that the waveform sample from channel 1 has exceeded the ipklvl value. 10 va ehf indicates that an interrupt occurred because the apparent energy register, vaenergy, is more than half full. 11 vaeof indicates that the apparent energy register has overflowed. 12 zxto indicates that an interrupt was caused by a missing zero crossi ng on the line voltage for a specified number of line cycles see the zero - crossing timeout section. 13 ppos indicates that the power has gone from negative to positive. 14 pneg indicates that the power has gone from positive to n egative. 15 reserved reserved. vaehf (vaenergy is half full) ppos (power negative to positive) reserved pneg (power positive to negative) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 7 4 5 6 2 3 0 1 15 14 13 12 11 10 aehf (active energy half full) sag (sag online voltage) cycend (end of linecyc half line cycles) wsmp (waveform samples data ready) zx (zero crossing) temp (temperature data ready) reset (end of software/hardware reset) aeof (active energy register overflow) zxto (zero-crossing timeout) vaeof (vaenergy overflow) pki (channel 1 sample above ipklvl) pkv (channel 2 sample above vpklvl) 04481-a-079 addr: 0x0a, 0x0b, 0x0c figure 87 . interrupt status/interrupt enable register
ade7763 data sheet rev . c | page 54 of 56 ch1os register (0 x 0d) the ch1os register is an 8 - bit, read/write enabled register. the msb of this register is used to switch the digital in tegrator on and off in channel 1, and bits 0 to 5 indicate the amount of offset correction in channel 1. table 13 summarizes the function of this register. table 13 . ch1os register bit location bit mnemonic description 0 to 5 offset the 6 lsbs of the ch1os register control the amount of dc offset corre c tion in the channel 1 adc. the 6 - bit offset corre c tion is sign and magnitude coded. bits 0 to 4 indicate the magnitude of the offset correction. bit 5 shows the sign of the offset correction. a 0 in bit 5 means the offset corre c tion is positive, and a 1 indicates the offset correction is negative. 6 not used this bit is not used. 7 integrator this bit is used to activate the digital integrator on channel 1. the digital integrator is switched on by setting this bit. this bit is set to 0 by default. digital integrator selection 1 = enable 0 = disable not used 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addr: 0x0d sign and magnitude coded offset correction bits 04481-a-078 figure 88 . channel 1 offset register
data sheet ade7763 rev. c | page 55 of 56 outline dimensions compliant t o jedec s t andards mo-150-ae 060106- a 20 1 1 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 se a ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 89 . 20 - lead shrink small outline package [ ssop] (rs - 20) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ade7763ars z ?40c to +85c 20- lead ssop rs -20 ade7763ars z rl ?40c to +85c 20- lead ssop rs -20 eval - ade7763z eb evaluation board 1 z = rohs compliant p art.
ade7763 data sheet rev . c | page 56 of 56 notes ? 2004 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04481 - 0- 1/13(c)

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